Struct stm32l4x6_hal::rcc::Rcc

pub struct Rcc {
    pub ahb: AHB,
    pub apb1: APB1,
    pub apb2: APB2,
    pub bdcr: BDCR,
    pub csr: CSR,
    pub cfgr: CFGR,
}

Constrained RCC peripheral

Fields

ahb: AHB

AMBA High-performance Bus (AHB) registers.

apb1: APB1

APB1 peripheral registers.

apb2: APB2

APB2 peripheral registers.

bdcr: BDCR

Backup domain registers.

csr: CSR

Control/status register.

cfgr: CFGR

HW clock configuration.

Trait Implementations

impl Constrain<Rcc> for RCC

fn constrain(self) -> Rcc

Create an RCC peripheral handle.

Per Reference Manual Ch. 6.2 the default System Clock source is MSI clock with frequency 4 MHz

The constrain method enables write access to the BDCR, and the freeze method disables it again. This is to enable changing LSE- and RTC-related settings.