pub enum RSF_AW {
Clear = 0,
}
Expand description
Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
Value on reset: 0
Variants§
Clear = 0
0: This flag is cleared by software by writing 0
Trait Implementations§
source§impl PartialEq for RSF_AW
impl PartialEq for RSF_AW
impl Copy for RSF_AW
impl StructuralPartialEq for RSF_AW
Auto Trait Implementations§
impl Freeze for RSF_AW
impl RefUnwindSafe for RSF_AW
impl Send for RSF_AW
impl Sync for RSF_AW
impl Unpin for RSF_AW
impl UnwindSafe for RSF_AW
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more