pub type CLKDIV_R = FieldReaderRaw<u8, u8>;
Expand description
Field CLKDIV
reader - Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)
Aliased Type§
struct CLKDIV_R { /* private fields */ }