Struct stm32h743::quadspi::quadspi_ccr::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn instruction(&self) -> INSTRUCTIONR[src]
Bits 0:7 - Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0.
pub fn imode(&self) -> IMODER[src]
Bits 8:9 - Instruction mode This field defines the instruction phase mode of operation: This field can be written only when BUSY = 0.
pub fn admode(&self) -> ADMODER[src]
Bits 10:11 - Address mode This field defines the address phase mode of operation: This field can be written only when BUSY = 0.
pub fn adsize(&self) -> ADSIZER[src]
Bits 12:13 - Address size This bit defines address size: This field can be written only when BUSY = 0.
pub fn abmode(&self) -> ABMODER[src]
Bits 14:15 - Alternate bytes mode This field defines the alternate-bytes phase mode of operation: This field can be written only when BUSY = 0.
pub fn absize(&self) -> ABSIZER[src]
Bits 16:17 - Alternate bytes size This bit defines alternate bytes size: This field can be written only when BUSY = 0.
pub fn dcyc(&self) -> DCYCR[src]
Bits 18:22 - Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0.
pub fn dmode(&self) -> DMODER[src]
Bits 24:25 - Data mode This field defines the data phases mode of operation: This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0.
pub fn fmode(&self) -> FMODER[src]
Bits 26:27 - Functional mode This field defines the QUADSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0.
pub fn sioo(&self) -> SIOOR[src]
Bit 28 - Send instruction only once mode See Section15.3.11: Sending the instruction only once on page13. This bit has no effect when IMODE = 00. This field can be written only when BUSY = 0.
pub fn dhhc(&self) -> DHHCR[src]
Bit 30 - DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: This feature is only active in DDR mode. This field can be written only when BUSY = 0.
pub fn ddrm(&self) -> DDRMR[src]
Bit 31 - Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: This field can be written only when BUSY = 0.