Struct stm32h743::fdcan1::fdcan_ir::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn rf0n(&self) -> RF0NR[src]
Bit 0 - Rx FIFO 0 New Message
pub fn rf0w(&self) -> RF0WR[src]
Bit 1 - Rx FIFO 0 Full
pub fn rf0f(&self) -> RF0FR[src]
Bit 2 - Rx FIFO 0 Full
pub fn rf0l(&self) -> RF0LR[src]
Bit 3 - Rx FIFO 0 Message Lost
pub fn rf1n(&self) -> RF1NR[src]
Bit 4 - Rx FIFO 1 New Message
pub fn rf1w(&self) -> RF1WR[src]
Bit 5 - Rx FIFO 1 Watermark Reached
pub fn rf1f(&self) -> RF1FR[src]
Bit 6 - Rx FIFO 1 Watermark Reached
pub fn rf1l(&self) -> RF1LR[src]
Bit 7 - Rx FIFO 1 Message Lost
pub fn hpm(&self) -> HPMR[src]
Bit 8 - High Priority Message
pub fn tc(&self) -> TCR[src]
Bit 9 - Transmission Completed
pub fn tcf(&self) -> TCFR[src]
Bit 10 - Transmission Cancellation Finished
pub fn tef(&self) -> TEFR[src]
Bit 11 - Tx FIFO Empty
pub fn tefn(&self) -> TEFNR[src]
Bit 12 - Tx Event FIFO New Entry
pub fn tefw(&self) -> TEFWR[src]
Bit 13 - Tx Event FIFO Watermark Reached
pub fn teff(&self) -> TEFFR[src]
Bit 14 - Tx Event FIFO Full
pub fn tefl(&self) -> TEFLR[src]
Bit 15 - Tx Event FIFO Element Lost
pub fn tsw(&self) -> TSWR[src]
Bit 16 - Timestamp Wraparound
pub fn mraf(&self) -> MRAFR[src]
Bit 17 - Message RAM Access Failure
pub fn too(&self) -> TOOR[src]
Bit 18 - Timeout Occurred
pub fn drx(&self) -> DRXR[src]
Bit 19 - Message stored to Dedicated Rx Buffer
pub fn elo(&self) -> ELOR[src]
Bit 22 - Error Logging Overflow
pub fn ep(&self) -> EPR[src]
Bit 23 - Error Passive
pub fn ew(&self) -> EWR[src]
Bit 24 - Warning Status
pub fn bo(&self) -> BOR[src]
Bit 25 - Bus_Off Status
pub fn wdi(&self) -> WDIR[src]
Bit 26 - Watchdog Interrupt
pub fn pea(&self) -> PEAR[src]
Bit 27 - Protocol Error in Arbitration Phase (Nominal Bit Time is used)
pub fn ped(&self) -> PEDR[src]
Bit 28 - Protocol Error in Data Phase (Data Bit Time is used)
pub fn ara(&self) -> ARAR[src]
Bit 29 - Access to Reserved Address