Module stm32h7::stm32h743v::dfsdm::ch::cfgr1

DFSDM channel configuration 0 register 1

Structs

CFGR1_SPEC

DFSDM channel configuration 0 register 1

R

Register CFGR1 reader

W

Register CFGR1 writer

Type Definitions

CHEN_R

Field CHEN reader - Channel 0 enable

CHEN_W

Field CHEN writer - Channel 0 enable

CHINSEL_R

Field CHINSEL reader - Channel inputs selection

CHINSEL_W

Field CHINSEL writer - Channel inputs selection

CKABEN_R

Field CKABEN reader - Clock absence detector enable on channel 0

CKABEN_W

Field CKABEN writer - Clock absence detector enable on channel 0

CKOUTDIV_R

Field CKOUTDIV reader - Output serial clock divider

CKOUTDIV_W

Field CKOUTDIV writer - Output serial clock divider

CKOUTSRC_R

Field CKOUTSRC reader - Output serial clock source selection

CKOUTSRC_W

Field CKOUTSRC writer - Output serial clock source selection

DATMPX_R

Field DATMPX reader - Input data multiplexer for channel 0

DATMPX_W

Field DATMPX writer - Input data multiplexer for channel 0

DATPACK_R

Field DATPACK reader - Data packing mode in DFSDM_CHDATINyR register

DATPACK_W

Field DATPACK writer - Data packing mode in DFSDM_CHDATINyR register

DFSDMEN_R

Field DFSDMEN reader - Global enable for DFSDM interface

DFSDMEN_W

Field DFSDMEN writer - Global enable for DFSDM interface

SCDEN_R

Field SCDEN reader - Short-circuit detector enable on channel 0

SCDEN_W

Field SCDEN writer - Short-circuit detector enable on channel 0

SITP_R

Field SITP reader - Serial interface type for channel 0

SITP_W

Field SITP writer - Serial interface type for channel 0

SPICKSEL_R

Field SPICKSEL reader - SPI clock select for channel 0

SPICKSEL_W

Field SPICKSEL writer - SPI clock select for channel 0