Struct stm32g4::stm32g441::fdcan::rwd::RWD_SPEC

pub struct RWD_SPEC;

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see rwd module

Trait Implementations

impl Readable for RWD_SPEC

read() method returns rwd::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for RWD_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for RWD_SPEC

reset() method sets RWD to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for RWD_SPEC

write(|w| ..) method takes rwd::W writer structure

type Writer = W

Writer type argument to write, et al.