Struct stm32g0::stm32g0c1::usb::cntr::W

pub struct W(_);

Register CNTR writer

Implementations

impl W

pub fn usbrst(&mut self) -> USBRST_W<'_, 0>

Bit 0 - USB Reset Device mode Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RESET bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RESET interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. Host mode Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software.

pub fn pdwn(&mut self) -> PDWN_W<'_, 1>

Bit 1 - Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used.

pub fn suspen(&mut self) -> SUSPEN_W<'_, 3>

Bit 3 - Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3Â ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set.

pub fn l2resume(&mut self) -> L2RESUME_W<'_, 4>

Bit 4 - L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt.

pub fn l1resume(&mut self) -> L1RESUME_W<'_, 5>

Bit 5 - L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume.

pub fn l1reqm(&mut self) -> L1REQM_W<'_, 7>

Bit 7 - LPM L1 state request interrupt mask

pub fn esofm(&mut self) -> ESOFM_W<'_, 8>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_, 9>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_, 10>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_, 11>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_, 12>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_, 13>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_, 14>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_, 15>

Bit 15 - Correct transfer interrupt mask

pub fn thr512m(&mut self) -> THR512M_W<'_, 16>

Bit 16 - 512 byte threshold interrupt mask

pub fn host(&mut self) -> HOST_W<'_, 31>

Bit 31 - HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CNTR_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CNTR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CNTR_SPEC>> for W

fn from(writer: W<CNTR_SPEC>) -> Self

Converts to this type from the input type.