Struct stm32g0::stm32g0c1::tim1::ccer::W

pub struct W(_);

Register CCER writer

Implementations

impl W

pub fn cc1e(&mut self) -> CC1E_W<'_, 0>

Bit 0 - Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated.

pub fn cc1p(&mut self) -> CC1P_W<'_, 1>

Bit 1 - Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.

pub fn cc1ne(&mut self) -> CC1NE_W<'_, 2>

Bit 2 - Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.

pub fn cc1np(&mut self) -> CC1NP_W<'_, 3>

Bit 3 - Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.

pub fn cc2e(&mut self) -> CC2E_W<'_, 4>

Bit 4 - Capture/Compare 2 output enable Refer to CC1E description

pub fn cc2p(&mut self) -> CC2P_W<'_, 5>

Bit 5 - Capture/Compare 2 output polarity Refer to CC1P description

pub fn cc2ne(&mut self) -> CC2NE_W<'_, 6>

Bit 6 - Capture/Compare 2 complementary output enable Refer to CC1NE description

pub fn cc2np(&mut self) -> CC2NP_W<'_, 7>

Bit 7 - Capture/Compare 2 complementary output polarity Refer to CC1NP description

pub fn cc3e(&mut self) -> CC3E_W<'_, 8>

Bit 8 - Capture/Compare 3 output enable Refer to CC1E description

pub fn cc3p(&mut self) -> CC3P_W<'_, 9>

Bit 9 - Capture/Compare 3 output polarity Refer to CC1P description

pub fn cc3ne(&mut self) -> CC3NE_W<'_, 10>

Bit 10 - Capture/Compare 3 complementary output enable Refer to CC1NE description

pub fn cc3np(&mut self) -> CC3NP_W<'_, 11>

Bit 11 - Capture/Compare 3 complementary output polarity Refer to CC1NP description

pub fn cc4e(&mut self) -> CC4E_W<'_, 12>

Bit 12 - Capture/Compare 4 output enable Refer to CC1E description

pub fn cc4p(&mut self) -> CC4P_W<'_, 13>

Bit 13 - Capture/Compare 4 output polarity Refer to CC1P description

pub fn cc4np(&mut self) -> CC4NP_W<'_, 15>

Bit 15 - Capture/Compare 4 complementary output polarity Refer to CC1NP description

pub fn cc5e(&mut self) -> CC5E_W<'_, 16>

Bit 16 - Capture/Compare 5 output enable Refer to CC1E description

pub fn cc5p(&mut self) -> CC5P_W<'_, 17>

Bit 17 - Capture/Compare 5 output polarity Refer to CC1P description

pub fn cc6e(&mut self) -> CC6E_W<'_, 20>

Bit 20 - Capture/Compare 6 output enable Refer to CC1E description

pub fn cc6p(&mut self) -> CC6P_W<'_, 21>

Bit 21 - Capture/Compare 6 output polarity Refer to CC1P description

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CCER_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CCER_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CCER_SPEC>> for W

fn from(writer: W<CCER_SPEC>) -> Self

Converts to this type from the input type.