Struct stm32g0::stm32g0c1::spi1::i2scfgr::W

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pub struct W(_);

Expand description

Register I2SCFGR writer

Implementations

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impl W

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pub fn chlen(&mut self) -> CHLEN_W<'_, 0>

Bit 0 - Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode.

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pub fn datlen(&mut self) -> DATLEN_W<'_, 1>

Bits 1:2 - Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.

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pub fn ckpol(&mut self) -> CKPOL_W<'_, 3>

Bit 3 - Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals.

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pub fn i2sstd(&mut self) -> I2SSTD_W<'_, 4>

Bits 4:5 - I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.

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pub fn pcmsync(&mut self) -> PCMSYNC_W<'_, 7>

Bit 7 - PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode.

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pub fn i2scfg(&mut self) -> I2SCFG_W<'_, 8>

Bits 8:9 - I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode.

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pub fn i2se(&mut self) -> I2SE_W<'_, 10>

Bit 10 - I2S enable Note: This bit is not used in SPI mode.

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pub fn i2smod(&mut self) -> I2SMOD_W<'_, 11>

Bit 11 - I2S mode selection Note: This bit should be configured when the SPI is disabled.

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pub fn astrten(&mut self) -> ASTRTEN_W<'_, 12>

Bit 12 - Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information.

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