Struct stm32g0::stm32g0c1::spi1::cr2::W

pub struct W(_);

Register CR2 writer

Implementations

impl W

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_, 0>

Bit 0 - Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_, 1>

Bit 1 - Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.

pub fn ssoe(&mut self) -> SSOE_W<'_, 2>

Bit 2 - SS output enable Note: This bit is not used in I2S mode and SPI TI mode.

pub fn nssp(&mut self) -> NSSP_W<'_, 3>

Bit 3 - NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.

pub fn frf(&mut self) -> FRF_W<'_, 4>

Bit 4 - Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.

pub fn errie(&mut self) -> ERRIE_W<'_, 5>

Bit 5 - Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).

pub fn rxneie(&mut self) -> RXNEIE_W<'_, 6>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_, 7>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_, 8>

Bits 8:11 - Data size These bits configure the data length for SPI transfers. If software attempts to write one of the “Not used” values, they are forced to the value “0111” (8-bit) Note: These bits are not used in I2S mode.

pub fn frxth(&mut self) -> FRXTH_W<'_, 12>

Bit 12 - FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_, 13>

Bit 13 - Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode.

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_, 14>

Bit 14 - Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CR2_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CR2_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CR2_SPEC>> for W

fn from(writer: W<CR2_SPEC>) -> Self

Converts to this type from the input type.