Struct stm32g0::stm32g0c1::spi1::cr1::W

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pub struct W(_);

Expand description

Register CR1 writer

Implementations

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impl W

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pub fn cpha(&mut self) -> CPHA_W<'_, 0>

Bit 0 - Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

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pub fn cpol(&mut self) -> CPOL_W<'_, 1>

Bit 1 - Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

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pub fn mstr(&mut self) -> MSTR_W<'_, 2>

Bit 2 - Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.

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pub fn br(&mut self) -> BR_W<'_, 3>

Bits 3:5 - Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.

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pub fn spe(&mut self) -> SPE_W<'_, 6>

Bit 6 - SPI enable Note: When disabling the SPI, follow the procedure described in SPI on pageÂ 1021. This bit is not used in I2S mode.

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pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_, 7>

Bit 7 - Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.

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pub fn ssi(&mut self) -> SSI_W<'_, 8>

Bit 8 - Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.

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pub fn ssm(&mut self) -> SSM_W<'_, 9>

Bit 9 - Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.

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pub fn rxonly(&mut self) -> RXONLY_W<'_, 10>

Bit 10 - Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.

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pub fn crcl(&mut self) -> CRCL_W<'_, 11>

Bit 11 - CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = ’0â) for correct operation. This bit is not used in I2S mode.

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pub fn crcnext(&mut self) -> CRCNEXT_W<'_, 12>

Bit 12 - Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode.

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pub fn crcen(&mut self) -> CRCEN_W<'_, 13>

Bit 13 - Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = ’0â) for correct operation. This bit is not used in I2S mode.

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pub fn bidioe(&mut self) -> BIDIOE_W<'_, 14>

Bit 14 - Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.

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pub fn bidimode(&mut self) -> BIDIMODE_W<'_, 15>

Bit 15 - Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.

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