pub struct W(_);
Expand description
Register CR1_enabled
writer
Implementations
sourceimpl W
impl W
sourcepub fn ue(&mut self) -> UE_W<'_, 0>
pub fn ue(&mut self) -> UE_W<'_, 0>
Bit 0 - LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.
sourcepub fn uesm(&mut self) -> UESM_W<'_, 1>
pub fn uesm(&mut self) -> UESM_W<'_, 1>
Bit 1 - LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode.
sourcepub fn re(&mut self) -> RE_W<'_, 2>
pub fn re(&mut self) -> RE_W<'_, 2>
Bit 2 - Receiver enable This bit enables the receiver. It is set and cleared by software.
sourcepub fn te(&mut self) -> TE_W<'_, 3>
pub fn te(&mut self) -> TE_W<'_, 3>
Bit 3 - Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (â0â followed by â1â) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts.
sourcepub fn idleie(&mut self) -> IDLEIE_W<'_, 4>
pub fn idleie(&mut self) -> IDLEIE_W<'_, 4>
Bit 4 - IDLE interrupt enable This bit is set and cleared by software.
sourcepub fn rxfneie(&mut self) -> RXFNEIE_W<'_, 5>
pub fn rxfneie(&mut self) -> RXFNEIE_W<'_, 5>
Bit 5 - RXFIFO not empty interrupt enable This bit is set and cleared by software.
sourcepub fn tcie(&mut self) -> TCIE_W<'_, 6>
pub fn tcie(&mut self) -> TCIE_W<'_, 6>
Bit 6 - Transmission complete interrupt enable This bit is set and cleared by software.
sourcepub fn txfnfie(&mut self) -> TXFNFIE_W<'_, 7>
pub fn txfnfie(&mut self) -> TXFNFIE_W<'_, 7>
Bit 7 - TXFIFO not full interrupt enable This bit is set and cleared by software.
sourcepub fn peie(&mut self) -> PEIE_W<'_, 8>
pub fn peie(&mut self) -> PEIE_W<'_, 8>
Bit 8 - PE interrupt enable This bit is set and cleared by software.
sourcepub fn ps(&mut self) -> PS_W<'_, 9>
pub fn ps(&mut self) -> PS_W<'_, 9>
Bit 9 - Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0).
sourcepub fn pce(&mut self) -> PCE_W<'_, 10>
pub fn pce(&mut self) -> PCE_W<'_, 10>
Bit 10 - Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0).
sourcepub fn wake(&mut self) -> WAKE_W<'_, 11>
pub fn wake(&mut self) -> WAKE_W<'_, 11>
Bit 11 - Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0).
sourcepub fn m0(&mut self) -> M0_W<'_, 12>
pub fn m0(&mut self) -> M0_W<'_, 12>
Bit 12 - Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UEÂ =Â 0).
sourcepub fn mme(&mut self) -> MME_W<'_, 13>
pub fn mme(&mut self) -> MME_W<'_, 13>
Bit 13 - Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software.
sourcepub fn cmie(&mut self) -> CMIE_W<'_, 14>
pub fn cmie(&mut self) -> CMIE_W<'_, 14>
Bit 14 - Character match interrupt enable This bit is set and cleared by software.
sourcepub fn dedt(&mut self) -> DEDT_W<'_, 16>
pub fn dedt(&mut self) -> DEDT_W<'_, 16>
Bits 16:20 - Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0).
sourcepub fn deat(&mut self) -> DEAT_W<'_, 21>
pub fn deat(&mut self) -> DEAT_W<'_, 21>
Bits 21:25 - Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer . This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0).
sourcepub fn m1(&mut self) -> M1_W<'_, 28>
pub fn m1(&mut self) -> M1_W<'_, 28>
Bit 28 - Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ’00â: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = ’01â: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = ’10â: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
sourcepub fn fifoen(&mut self) -> FIFOEN_W<'_, 29>
pub fn fifoen(&mut self) -> FIFOEN_W<'_, 29>
Bit 29 - FIFO mode enable This bit is set and cleared by software.
sourcepub fn txfeie(&mut self) -> TXFEIE_W<'_, 30>
pub fn txfeie(&mut self) -> TXFEIE_W<'_, 30>
Bit 30 - TXFIFO empty interrupt enable This bit is set and cleared by software.
Methods from Deref<Target = W<CR1_ENABLED_SPEC>>
Trait Implementations
sourceimpl From<W<CR1_ENABLED_SPEC>> for W
impl From<W<CR1_ENABLED_SPEC>> for W
sourcefn from(writer: W<CR1_ENABLED_SPEC>) -> Self
fn from(writer: W<CR1_ENABLED_SPEC>) -> Self
Converts to this type from the input type.
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more