Struct stm32g0::stm32g0c1::adc::cfgr2::W

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pub struct W(_);

Expand description

Register CFGR2 writer

Implementations

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impl W

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pub fn ovse(&mut self) -> OVSE_W<'_, 0>

Bit 0 - Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).

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pub fn ovsr(&mut self) -> OVSR_W<'_, 2>

Bits 2:4 - Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).

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pub fn ovss(&mut self) -> OVSS_W<'_, 5>

Bits 5:8 - Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).

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pub fn tovs(&mut self) -> TOVS_W<'_, 9>

Bit 9 - Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).

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pub fn lftrig(&mut self) -> LFTRIG_W<'_, 29>

Bit 29 - Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

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pub fn ckmode(&mut self) -> CKMODE_W<'_, 30>

Bits 30:31 - ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).

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