Struct stm32g0::stm32g0b0::usart1::cr1_fifo_disabled::R

pub struct R(_);

Register CR1_FIFO_DISABLED reader

Implementations

impl R

pub fn ue(&self) -> UE_R

Bit 0 - USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable This bit enables the receiver. It is set and cleared by software.

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (’0’ followed by ’1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to ’1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable This bit is set and cleared by software.

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - Receive data register not empty This bit is set and cleared by software.

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable This bit is set and cleared by software.

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Transmit data register empty This bit is set and cleared by software.

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable This bit is set and cleared by software.

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).

pub fn m0(&self) -> M0_R

Bit 12 - Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable This bit is set and cleared by software.

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn deat(&self) -> DEAT_R

Bits 21:25 - Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

pub fn m1(&self) -> M1_R

Bit 28 - Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ’00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = ’01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = ’10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.

Methods from Deref<Target = R<CR1_FIFO_DISABLED_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CR1_FIFO_DISABLED_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CR1_FIFO_DISABLED_SPEC>> for R

fn from(reader: R<CR1_FIFO_DISABLED_SPEC>) -> Self

Converts to this type from the input type.