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#[doc = "Reader of register AHBENR"] pub type R = crate::R<u32, super::AHBENR>; #[doc = "Writer for register AHBENR"] pub type W = crate::W<u32, super::AHBENR>; #[doc = "Register AHBENR `reset()`'s with value 0"] impl crate::ResetValue for super::AHBENR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `DMAEN`"] pub type DMAEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAEN`"] pub struct DMAEN_W<'a> { w: &'a mut W, } impl<'a> DMAEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `FLASHEN`"] pub type FLASHEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `FLASHEN`"] pub struct FLASHEN_W<'a> { w: &'a mut W, } impl<'a> FLASHEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `CRCEN`"] pub type CRCEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CRCEN`"] pub struct CRCEN_W<'a> { w: &'a mut W, } impl<'a> CRCEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } impl R { #[doc = "Bit 0 - DMA clock enable"] #[inline(always)] pub fn dmaen(&self) -> DMAEN_R { DMAEN_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 8 - Flash memory interface clock enable"] #[inline(always)] pub fn flashen(&self) -> FLASHEN_R { FLASHEN_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 12 - CRC clock enable"] #[inline(always)] pub fn crcen(&self) -> CRCEN_R { CRCEN_R::new(((self.bits >> 12) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - DMA clock enable"] #[inline(always)] pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W { w: self } } #[doc = "Bit 8 - Flash memory interface clock enable"] #[inline(always)] pub fn flashen(&mut self) -> FLASHEN_W { FLASHEN_W { w: self } } #[doc = "Bit 12 - CRC clock enable"] #[inline(always)] pub fn crcen(&mut self) -> CRCEN_W { CRCEN_W { w: self } } }