Struct stm32f7xx_hal::pac::tim2::ccmr2_output::OC3M_W

pub struct OC3M_W<'a> { /* fields omitted */ }

Write proxy for field OC3M

Implementations

impl<'a> OC3M_W<'a>

pub fn variant(self, variant: OC4M_A) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Writes variant to the field

pub fn frozen(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs

pub fn active_on_match(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register

pub fn inactive_on_match(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register

pub fn toggle(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF toggles when TIMx_CNT=TIMx_CCRy

pub fn force_inactive(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF is forced low

pub fn force_active(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF is forced high

pub fn pwm_mode1(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active

pub fn pwm_mode2(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Inversely to PwmMode1

pub fn opm_mode1(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive

pub fn opm_mode2(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Inversely to OpmMode1

pub fn combined_pwm_mode1(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF

pub fn combined_pwm_mode2(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF

pub fn asymmetric_pwm_mode1(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down

pub fn asymmetric_pwm_mode2(self) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down

pub unsafe fn bits(self, value: u8) -> &'a mut W<u32, Reg<u32, _CCMR2_OUTPUT>>

Writes raw bits to the field