Enum stm32f7xx_hal::pac::tim2::ccmr1_output::OC2PE_A [−][src]
pub enum OC2PE_A {
DISABLED,
ENABLED,
}
Expand description
OC2PE
Value on reset: 0
Variants
0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event