Enum stm32f7xx_hal::pac::tim2::ccmr1_output::OC2M_A [−][src]
#[repr(u8)]
pub enum OC2M_A {
Show 14 variants
FROZEN,
ACTIVEONMATCH,
INACTIVEONMATCH,
TOGGLE,
FORCEINACTIVE,
FORCEACTIVE,
PWMMODE1,
PWMMODE2,
OPMMODE1,
OPMMODE2,
COMBINEDPWMMODE1,
COMBINEDPWMMODE2,
ASYMMETRICPWMMODE1,
ASYMMETRICPWMMODE2,
}
Expand description
OC2M
Value on reset: 0
Variants
0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: OCyREF is forced low
5: OCyREF is forced high
6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: Inversely to PwmMode1
8: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
9: Inversely to OpmMode1
12: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
13: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
14: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
15: OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down