Struct stm32f7xx_hal::pac::otg_hs_host::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 103 fields
pub otg_hs_hcfg: Reg<u32, _OTG_HS_HCFG>,
pub otg_hs_hfir: Reg<u32, _OTG_HS_HFIR>,
pub otg_hs_hfnum: Reg<u32, _OTG_HS_HFNUM>,
pub otg_hs_hptxsts: Reg<u32, _OTG_HS_HPTXSTS>,
pub otg_hs_haint: Reg<u32, _OTG_HS_HAINT>,
pub otg_hs_haintmsk: Reg<u32, _OTG_HS_HAINTMSK>,
pub otg_hs_hprt: Reg<u32, _OTG_HS_HPRT>,
pub otg_hs_hcchar0: Reg<u32, _OTG_HS_HCCHAR0>,
pub otg_hs_hcsplt0: Reg<u32, _OTG_HS_HCSPLT0>,
pub otg_hs_hcint0: Reg<u32, _OTG_HS_HCINT0>,
pub otg_hs_hcintmsk0: Reg<u32, _OTG_HS_HCINTMSK0>,
pub otg_hs_hctsiz0: Reg<u32, _OTG_HS_HCTSIZ0>,
pub otg_hs_hcdma0: Reg<u32, _OTG_HS_HCDMA0>,
pub otg_hs_hcchar1: Reg<u32, _OTG_HS_HCCHAR1>,
pub otg_hs_hcsplt1: Reg<u32, _OTG_HS_HCSPLT1>,
pub otg_hs_hcint1: Reg<u32, _OTG_HS_HCINT1>,
pub otg_hs_hcintmsk1: Reg<u32, _OTG_HS_HCINTMSK1>,
pub otg_hs_hctsiz1: Reg<u32, _OTG_HS_HCTSIZ1>,
pub otg_hs_hcdma1: Reg<u32, _OTG_HS_HCDMA1>,
pub otg_hs_hcchar2: Reg<u32, _OTG_HS_HCCHAR2>,
pub otg_hs_hcsplt2: Reg<u32, _OTG_HS_HCSPLT2>,
pub otg_hs_hcint2: Reg<u32, _OTG_HS_HCINT2>,
pub otg_hs_hcintmsk2: Reg<u32, _OTG_HS_HCINTMSK2>,
pub otg_hs_hctsiz2: Reg<u32, _OTG_HS_HCTSIZ2>,
pub otg_hs_hcdma2: Reg<u32, _OTG_HS_HCDMA2>,
pub otg_hs_hcchar3: Reg<u32, _OTG_HS_HCCHAR3>,
pub otg_hs_hcsplt3: Reg<u32, _OTG_HS_HCSPLT3>,
pub otg_hs_hcint3: Reg<u32, _OTG_HS_HCINT3>,
pub otg_hs_hcintmsk3: Reg<u32, _OTG_HS_HCINTMSK3>,
pub otg_hs_hctsiz3: Reg<u32, _OTG_HS_HCTSIZ3>,
pub otg_hs_hcdma3: Reg<u32, _OTG_HS_HCDMA3>,
pub otg_hs_hcchar4: Reg<u32, _OTG_HS_HCCHAR4>,
pub otg_hs_hcsplt4: Reg<u32, _OTG_HS_HCSPLT4>,
pub otg_hs_hcint4: Reg<u32, _OTG_HS_HCINT4>,
pub otg_hs_hcintmsk4: Reg<u32, _OTG_HS_HCINTMSK4>,
pub otg_hs_hctsiz4: Reg<u32, _OTG_HS_HCTSIZ4>,
pub otg_hs_hcdma4: Reg<u32, _OTG_HS_HCDMA4>,
pub otg_hs_hcchar5: Reg<u32, _OTG_HS_HCCHAR5>,
pub otg_hs_hcsplt5: Reg<u32, _OTG_HS_HCSPLT5>,
pub otg_hs_hcint5: Reg<u32, _OTG_HS_HCINT5>,
pub otg_hs_hcintmsk5: Reg<u32, _OTG_HS_HCINTMSK5>,
pub otg_hs_hctsiz5: Reg<u32, _OTG_HS_HCTSIZ5>,
pub otg_hs_hcdma5: Reg<u32, _OTG_HS_HCDMA5>,
pub otg_hs_hcchar6: Reg<u32, _OTG_HS_HCCHAR6>,
pub otg_hs_hcsplt6: Reg<u32, _OTG_HS_HCSPLT6>,
pub otg_hs_hcint6: Reg<u32, _OTG_HS_HCINT6>,
pub otg_hs_hcintmsk6: Reg<u32, _OTG_HS_HCINTMSK6>,
pub otg_hs_hctsiz6: Reg<u32, _OTG_HS_HCTSIZ6>,
pub otg_hs_hcdma6: Reg<u32, _OTG_HS_HCDMA6>,
pub otg_hs_hcchar7: Reg<u32, _OTG_HS_HCCHAR7>,
pub otg_hs_hcsplt7: Reg<u32, _OTG_HS_HCSPLT7>,
pub otg_hs_hcint7: Reg<u32, _OTG_HS_HCINT7>,
pub otg_hs_hcintmsk7: Reg<u32, _OTG_HS_HCINTMSK7>,
pub otg_hs_hctsiz7: Reg<u32, _OTG_HS_HCTSIZ7>,
pub otg_hs_hcdma7: Reg<u32, _OTG_HS_HCDMA7>,
pub otg_hs_hcchar8: Reg<u32, _OTG_HS_HCCHAR8>,
pub otg_hs_hcsplt8: Reg<u32, _OTG_HS_HCSPLT8>,
pub otg_hs_hcint8: Reg<u32, _OTG_HS_HCINT8>,
pub otg_hs_hcintmsk8: Reg<u32, _OTG_HS_HCINTMSK8>,
pub otg_hs_hctsiz8: Reg<u32, _OTG_HS_HCTSIZ8>,
pub otg_hs_hcdma8: Reg<u32, _OTG_HS_HCDMA8>,
pub otg_hs_hcchar9: Reg<u32, _OTG_HS_HCCHAR9>,
pub otg_hs_hcsplt9: Reg<u32, _OTG_HS_HCSPLT9>,
pub otg_hs_hcint9: Reg<u32, _OTG_HS_HCINT9>,
pub otg_hs_hcintmsk9: Reg<u32, _OTG_HS_HCINTMSK9>,
pub otg_hs_hctsiz9: Reg<u32, _OTG_HS_HCTSIZ9>,
pub otg_hs_hcdma9: Reg<u32, _OTG_HS_HCDMA9>,
pub otg_hs_hcchar10: Reg<u32, _OTG_HS_HCCHAR10>,
pub otg_hs_hcsplt10: Reg<u32, _OTG_HS_HCSPLT10>,
pub otg_hs_hcint10: Reg<u32, _OTG_HS_HCINT10>,
pub otg_hs_hcintmsk10: Reg<u32, _OTG_HS_HCINTMSK10>,
pub otg_hs_hctsiz10: Reg<u32, _OTG_HS_HCTSIZ10>,
pub otg_hs_hcdma10: Reg<u32, _OTG_HS_HCDMA10>,
pub otg_hs_hcchar11: Reg<u32, _OTG_HS_HCCHAR11>,
pub otg_hs_hcsplt11: Reg<u32, _OTG_HS_HCSPLT11>,
pub otg_hs_hcint11: Reg<u32, _OTG_HS_HCINT11>,
pub otg_hs_hcintmsk11: Reg<u32, _OTG_HS_HCINTMSK11>,
pub otg_hs_hctsiz11: Reg<u32, _OTG_HS_HCTSIZ11>,
pub otg_hs_hcdma11: Reg<u32, _OTG_HS_HCDMA11>,
pub otg_hs_hcchar12: Reg<u32, _OTG_HS_HCCHAR12>,
pub otg_hs_hcsplt12: Reg<u32, _OTG_HS_HCSPLT12>,
pub otg_hs_hcint12: Reg<u32, _OTG_HS_HCINT12>,
pub otg_hs_hcintmsk12: Reg<u32, _OTG_HS_HCINTMSK12>,
pub otg_hs_hctsiz12: Reg<u32, _OTG_HS_HCTSIZ12>,
pub otg_hs_hcdma12: Reg<u32, _OTG_HS_HCDMA12>,
pub otg_hs_hcchar13: Reg<u32, _OTG_HS_HCCHAR13>,
pub otg_hs_hcsplt13: Reg<u32, _OTG_HS_HCSPLT13>,
pub otg_hs_hcint13: Reg<u32, _OTG_HS_HCINT13>,
pub otg_hs_hcintmsk13: Reg<u32, _OTG_HS_HCINTMSK13>,
pub otg_hs_hctsiz13: Reg<u32, _OTG_HS_HCTSIZ13>,
pub otg_hs_hcdma13: Reg<u32, _OTG_HS_HCDMA13>,
pub otg_hs_hcchar14: Reg<u32, _OTG_HS_HCCHAR14>,
pub otg_hs_hcsplt14: Reg<u32, _OTG_HS_HCSPLT14>,
pub otg_hs_hcint14: Reg<u32, _OTG_HS_HCINT14>,
pub otg_hs_hcintmsk14: Reg<u32, _OTG_HS_HCINTMSK14>,
pub otg_hs_hctsiz14: Reg<u32, _OTG_HS_HCTSIZ14>,
pub otg_hs_hcdma14: Reg<u32, _OTG_HS_HCDMA14>,
pub otg_hs_hcchar15: Reg<u32, _OTG_HS_HCCHAR15>,
pub otg_hs_hcsplt15: Reg<u32, _OTG_HS_HCSPLT15>,
pub otg_hs_hcint15: Reg<u32, _OTG_HS_HCINT15>,
pub otg_hs_hcintmsk15: Reg<u32, _OTG_HS_HCINTMSK15>,
pub otg_hs_hctsiz15: Reg<u32, _OTG_HS_HCTSIZ15>,
pub otg_hs_hcdma15: Reg<u32, _OTG_HS_HCDMA15>,
// some fields omitted
}Expand description
Register block
Fields
otg_hs_hcfg: Reg<u32, _OTG_HS_HCFG>0x00 - OTG_HS host configuration register
otg_hs_hfir: Reg<u32, _OTG_HS_HFIR>0x04 - OTG_HS Host frame interval register
otg_hs_hfnum: Reg<u32, _OTG_HS_HFNUM>0x08 - OTG_HS host frame number/frame time remaining register
otg_hs_hptxsts: Reg<u32, _OTG_HS_HPTXSTS>0x10 - OTG_HS_Host periodic transmit FIFO/queue status register
otg_hs_haint: Reg<u32, _OTG_HS_HAINT>0x14 - OTG_HS Host all channels interrupt register
otg_hs_haintmsk: Reg<u32, _OTG_HS_HAINTMSK>0x18 - OTG_HS host all channels interrupt mask register
otg_hs_hprt: Reg<u32, _OTG_HS_HPRT>0x40 - OTG_HS host port control and status register
otg_hs_hcchar0: Reg<u32, _OTG_HS_HCCHAR0>0x100 - OTG_HS host channel-0 characteristics register
otg_hs_hcsplt0: Reg<u32, _OTG_HS_HCSPLT0>0x104 - OTG_HS host channel-0 split control register
otg_hs_hcint0: Reg<u32, _OTG_HS_HCINT0>0x108 - OTG_HS host channel-11 interrupt register
otg_hs_hcintmsk0: Reg<u32, _OTG_HS_HCINTMSK0>0x10c - OTG_HS host channel-11 interrupt mask register
otg_hs_hctsiz0: Reg<u32, _OTG_HS_HCTSIZ0>0x110 - OTG_HS host channel-11 transfer size register
otg_hs_hcdma0: Reg<u32, _OTG_HS_HCDMA0>0x114 - OTG_HS host channel-0 DMA address register
otg_hs_hcchar1: Reg<u32, _OTG_HS_HCCHAR1>0x120 - OTG_HS host channel-1 characteristics register
otg_hs_hcsplt1: Reg<u32, _OTG_HS_HCSPLT1>0x124 - OTG_HS host channel-1 split control register
otg_hs_hcint1: Reg<u32, _OTG_HS_HCINT1>0x128 - OTG_HS host channel-1 interrupt register
otg_hs_hcintmsk1: Reg<u32, _OTG_HS_HCINTMSK1>0x12c - OTG_HS host channel-1 interrupt mask register
otg_hs_hctsiz1: Reg<u32, _OTG_HS_HCTSIZ1>0x130 - OTG_HS host channel-1 transfer size register
otg_hs_hcdma1: Reg<u32, _OTG_HS_HCDMA1>0x134 - OTG_HS host channel-1 DMA address register
otg_hs_hcchar2: Reg<u32, _OTG_HS_HCCHAR2>0x140 - OTG_HS host channel-2 characteristics register
otg_hs_hcsplt2: Reg<u32, _OTG_HS_HCSPLT2>0x144 - OTG_HS host channel-2 split control register
otg_hs_hcint2: Reg<u32, _OTG_HS_HCINT2>0x148 - OTG_HS host channel-2 interrupt register
otg_hs_hcintmsk2: Reg<u32, _OTG_HS_HCINTMSK2>0x14c - OTG_HS host channel-2 interrupt mask register
otg_hs_hctsiz2: Reg<u32, _OTG_HS_HCTSIZ2>0x150 - OTG_HS host channel-2 transfer size register
otg_hs_hcdma2: Reg<u32, _OTG_HS_HCDMA2>0x154 - OTG_HS host channel-2 DMA address register
otg_hs_hcchar3: Reg<u32, _OTG_HS_HCCHAR3>0x160 - OTG_HS host channel-3 characteristics register
otg_hs_hcsplt3: Reg<u32, _OTG_HS_HCSPLT3>0x164 - OTG_HS host channel-3 split control register
otg_hs_hcint3: Reg<u32, _OTG_HS_HCINT3>0x168 - OTG_HS host channel-3 interrupt register
otg_hs_hcintmsk3: Reg<u32, _OTG_HS_HCINTMSK3>0x16c - OTG_HS host channel-3 interrupt mask register
otg_hs_hctsiz3: Reg<u32, _OTG_HS_HCTSIZ3>0x170 - OTG_HS host channel-3 transfer size register
otg_hs_hcdma3: Reg<u32, _OTG_HS_HCDMA3>0x174 - OTG_HS host channel-3 DMA address register
otg_hs_hcchar4: Reg<u32, _OTG_HS_HCCHAR4>0x180 - OTG_HS host channel-4 characteristics register
otg_hs_hcsplt4: Reg<u32, _OTG_HS_HCSPLT4>0x184 - OTG_HS host channel-4 split control register
otg_hs_hcint4: Reg<u32, _OTG_HS_HCINT4>0x188 - OTG_HS host channel-4 interrupt register
otg_hs_hcintmsk4: Reg<u32, _OTG_HS_HCINTMSK4>0x18c - OTG_HS host channel-4 interrupt mask register
otg_hs_hctsiz4: Reg<u32, _OTG_HS_HCTSIZ4>0x190 - OTG_HS host channel-4 transfer size register
otg_hs_hcdma4: Reg<u32, _OTG_HS_HCDMA4>0x194 - OTG_HS host channel-4 DMA address register
otg_hs_hcchar5: Reg<u32, _OTG_HS_HCCHAR5>0x1a0 - OTG_HS host channel-5 characteristics register
otg_hs_hcsplt5: Reg<u32, _OTG_HS_HCSPLT5>0x1a4 - OTG_HS host channel-5 split control register
otg_hs_hcint5: Reg<u32, _OTG_HS_HCINT5>0x1a8 - OTG_HS host channel-5 interrupt register
otg_hs_hcintmsk5: Reg<u32, _OTG_HS_HCINTMSK5>0x1ac - OTG_HS host channel-5 interrupt mask register
otg_hs_hctsiz5: Reg<u32, _OTG_HS_HCTSIZ5>0x1b0 - OTG_HS host channel-5 transfer size register
otg_hs_hcdma5: Reg<u32, _OTG_HS_HCDMA5>0x1b4 - OTG_HS host channel-5 DMA address register
otg_hs_hcchar6: Reg<u32, _OTG_HS_HCCHAR6>0x1c0 - OTG_HS host channel-6 characteristics register
otg_hs_hcsplt6: Reg<u32, _OTG_HS_HCSPLT6>0x1c4 - OTG_HS host channel-6 split control register
otg_hs_hcint6: Reg<u32, _OTG_HS_HCINT6>0x1c8 - OTG_HS host channel-6 interrupt register
otg_hs_hcintmsk6: Reg<u32, _OTG_HS_HCINTMSK6>0x1cc - OTG_HS host channel-6 interrupt mask register
otg_hs_hctsiz6: Reg<u32, _OTG_HS_HCTSIZ6>0x1d0 - OTG_HS host channel-6 transfer size register
otg_hs_hcdma6: Reg<u32, _OTG_HS_HCDMA6>0x1d4 - OTG_HS host channel-6 DMA address register
otg_hs_hcchar7: Reg<u32, _OTG_HS_HCCHAR7>0x1e0 - OTG_HS host channel-7 characteristics register
otg_hs_hcsplt7: Reg<u32, _OTG_HS_HCSPLT7>0x1e4 - OTG_HS host channel-7 split control register
otg_hs_hcint7: Reg<u32, _OTG_HS_HCINT7>0x1e8 - OTG_HS host channel-7 interrupt register
otg_hs_hcintmsk7: Reg<u32, _OTG_HS_HCINTMSK7>0x1ec - OTG_HS host channel-7 interrupt mask register
otg_hs_hctsiz7: Reg<u32, _OTG_HS_HCTSIZ7>0x1f0 - OTG_HS host channel-7 transfer size register
otg_hs_hcdma7: Reg<u32, _OTG_HS_HCDMA7>0x1f4 - OTG_HS host channel-7 DMA address register
otg_hs_hcchar8: Reg<u32, _OTG_HS_HCCHAR8>0x200 - OTG_HS host channel-8 characteristics register
otg_hs_hcsplt8: Reg<u32, _OTG_HS_HCSPLT8>0x204 - OTG_HS host channel-8 split control register
otg_hs_hcint8: Reg<u32, _OTG_HS_HCINT8>0x208 - OTG_HS host channel-8 interrupt register
otg_hs_hcintmsk8: Reg<u32, _OTG_HS_HCINTMSK8>0x20c - OTG_HS host channel-8 interrupt mask register
otg_hs_hctsiz8: Reg<u32, _OTG_HS_HCTSIZ8>0x210 - OTG_HS host channel-8 transfer size register
otg_hs_hcdma8: Reg<u32, _OTG_HS_HCDMA8>0x214 - OTG_HS host channel-8 DMA address register
otg_hs_hcchar9: Reg<u32, _OTG_HS_HCCHAR9>0x220 - OTG_HS host channel-9 characteristics register
otg_hs_hcsplt9: Reg<u32, _OTG_HS_HCSPLT9>0x224 - OTG_HS host channel-9 split control register
otg_hs_hcint9: Reg<u32, _OTG_HS_HCINT9>0x228 - OTG_HS host channel-9 interrupt register
otg_hs_hcintmsk9: Reg<u32, _OTG_HS_HCINTMSK9>0x22c - OTG_HS host channel-9 interrupt mask register
otg_hs_hctsiz9: Reg<u32, _OTG_HS_HCTSIZ9>0x230 - OTG_HS host channel-9 transfer size register
otg_hs_hcdma9: Reg<u32, _OTG_HS_HCDMA9>0x234 - OTG_HS host channel-9 DMA address register
otg_hs_hcchar10: Reg<u32, _OTG_HS_HCCHAR10>0x240 - OTG_HS host channel-10 characteristics register
otg_hs_hcsplt10: Reg<u32, _OTG_HS_HCSPLT10>0x244 - OTG_HS host channel-10 split control register
otg_hs_hcint10: Reg<u32, _OTG_HS_HCINT10>0x248 - OTG_HS host channel-10 interrupt register
otg_hs_hcintmsk10: Reg<u32, _OTG_HS_HCINTMSK10>0x24c - OTG_HS host channel-10 interrupt mask register
otg_hs_hctsiz10: Reg<u32, _OTG_HS_HCTSIZ10>0x250 - OTG_HS host channel-10 transfer size register
otg_hs_hcdma10: Reg<u32, _OTG_HS_HCDMA10>0x254 - OTG_HS host channel-10 DMA address register
otg_hs_hcchar11: Reg<u32, _OTG_HS_HCCHAR11>0x260 - OTG_HS host channel-11 characteristics register
otg_hs_hcsplt11: Reg<u32, _OTG_HS_HCSPLT11>0x264 - OTG_HS host channel-11 split control register
otg_hs_hcint11: Reg<u32, _OTG_HS_HCINT11>0x268 - OTG_HS host channel-11 interrupt register
otg_hs_hcintmsk11: Reg<u32, _OTG_HS_HCINTMSK11>0x26c - OTG_HS host channel-11 interrupt mask register
otg_hs_hctsiz11: Reg<u32, _OTG_HS_HCTSIZ11>0x270 - OTG_HS host channel-11 transfer size register
otg_hs_hcdma11: Reg<u32, _OTG_HS_HCDMA11>0x274 - OTG_HS host channel-11 DMA address register
otg_hs_hcchar12: Reg<u32, _OTG_HS_HCCHAR12>0x278 - OTG_HS host channel-12 characteristics register
otg_hs_hcsplt12: Reg<u32, _OTG_HS_HCSPLT12>0x27c - OTG_HS host channel-12 split control register
otg_hs_hcint12: Reg<u32, _OTG_HS_HCINT12>0x280 - OTG_HS host channel-12 interrupt register
otg_hs_hcintmsk12: Reg<u32, _OTG_HS_HCINTMSK12>0x284 - OTG_HS host channel-12 interrupt mask register
otg_hs_hctsiz12: Reg<u32, _OTG_HS_HCTSIZ12>0x288 - OTG_HS host channel-12 transfer size register
otg_hs_hcdma12: Reg<u32, _OTG_HS_HCDMA12>0x28c - OTG_HS host channel-12 DMA address register
otg_hs_hcchar13: Reg<u32, _OTG_HS_HCCHAR13>0x290 - OTG_HS host channel-13 characteristics register
otg_hs_hcsplt13: Reg<u32, _OTG_HS_HCSPLT13>0x294 - OTG_HS host channel-13 split control register
otg_hs_hcint13: Reg<u32, _OTG_HS_HCINT13>0x298 - OTG_HS host channel-13 interrupt register
otg_hs_hcintmsk13: Reg<u32, _OTG_HS_HCINTMSK13>0x29c - OTG_HS host channel-13 interrupt mask register
otg_hs_hctsiz13: Reg<u32, _OTG_HS_HCTSIZ13>0x2a0 - OTG_HS host channel-13 transfer size register
otg_hs_hcdma13: Reg<u32, _OTG_HS_HCDMA13>0x2a4 - OTG_HS host channel-13 DMA address register
otg_hs_hcchar14: Reg<u32, _OTG_HS_HCCHAR14>0x2a8 - OTG_HS host channel-14 characteristics register
otg_hs_hcsplt14: Reg<u32, _OTG_HS_HCSPLT14>0x2ac - OTG_HS host channel-14 split control register
otg_hs_hcint14: Reg<u32, _OTG_HS_HCINT14>0x2b0 - OTG_HS host channel-14 interrupt register
otg_hs_hcintmsk14: Reg<u32, _OTG_HS_HCINTMSK14>0x2b4 - OTG_HS host channel-14 interrupt mask register
otg_hs_hctsiz14: Reg<u32, _OTG_HS_HCTSIZ14>0x2b8 - OTG_HS host channel-14 transfer size register
otg_hs_hcdma14: Reg<u32, _OTG_HS_HCDMA14>0x2bc - OTG_HS host channel-14 DMA address register
otg_hs_hcchar15: Reg<u32, _OTG_HS_HCCHAR15>0x2c0 - OTG_HS host channel-15 characteristics register
otg_hs_hcsplt15: Reg<u32, _OTG_HS_HCSPLT15>0x2c4 - OTG_HS host channel-15 split control register
otg_hs_hcint15: Reg<u32, _OTG_HS_HCINT15>0x2c8 - OTG_HS host channel-15 interrupt register
otg_hs_hcintmsk15: Reg<u32, _OTG_HS_HCINTMSK15>0x2cc - OTG_HS host channel-15 interrupt mask register
otg_hs_hctsiz15: Reg<u32, _OTG_HS_HCTSIZ15>0x2d0 - OTG_HS host channel-15 transfer size register
otg_hs_hcdma15: Reg<u32, _OTG_HS_HCDMA15>0x2d4 - OTG_HS host channel-15 DMA address register