Struct stm32f7xx_hal::rcc::CFGR [−][src]
pub struct CFGR { /* fields omitted */ }Expand description
Clock configuration register.
Implementations
Sets HCLK frequency.
The HCLK is used for the AHB bus, core, memory and DMA.
Panics
Panics if the frequency is larger than 216 MHz.
Sets the SYSCLK frequency.
This sets the SYSCLK frequency and sets up the USB clock if defined. The provided frequency must be between 12.5 Mhz and 216 Mhz. 12.5 Mhz is the VCO minimum frequency and SYSCLK PLLP divider limitation. If the ethernet peripheral is on, the user should set a frequency higher than 25 Mhz.
Panics
Panics if the frequency is not between 12.5 MHz and 216 MHz.
Sets the PCLK1 clock (APB1 clock).
If this method isn’t called the maximum allowed frequency is used for PCLK1.
Panics
Panics if the frequency is not between 12.5 MHz and 54 MHz.
Sets PCLK2 clock (APB2 clock).
If this method isn’t called the maximum allowed frequency is used for PCLK2.
Panics
Panics if the frequency is not between 12.5 MHz and 108 MHz.
Sets the 48 MHz clock source to the main PLL.
Sets the PLL multiplication factor for the main PLL.
Panics
Panics if the multiplication factor isn’t between 50 and 432.
Sets the PLL division factor for the 48 MHz clock.
Panics
Panics if the division factor isn’t between 2 and 15.
Configures the default clock settings.
Set SYSCLK as 216 Mhz and setup USB clock if defined.
Configure the “mandatory” clocks (sysclk, hclk, pclk1 and pclk2') and return them via the Clocks` struct.
The user shouldn’t call freeze more than once as the clocks parameters cannot be changed after the clocks have started.
The implementation makes the following choice: HSI is always chosen over HSE except when HSE is provided. When HSE is provided, HSE is used wherever it is possible.