Trait stm32f7xx_hal::dma::Target[−][src]

pub trait Target {
    type Instance: Deref<Target = RegisterBlock>;
    type Stream: Stream;
    type Channel: Channel;

    const INTERRUPT: Interrupt;
}

Expand description

Implemented for all peripheral APIs that support DMA transfers

This is an internal trait. End users neither need to implement it, nor use it directly.

Associated Types

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type Instance: Deref<Target = RegisterBlock>

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type Stream: Stream

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type Channel: Channel

Associated Constants

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const INTERRUPT: Interrupt

Implementors

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impl Target for RxTx<QUADSPI>

type Instance = DMA2

type Stream = Stream7<DMA2>

type Channel = Channel3

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<UART4>

type Instance = DMA1

type Stream = Stream2<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<UART5>

type Instance = DMA1

type Stream = Stream0<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<UART7>

type Instance = DMA1

type Stream = Stream3<DMA1>

type Channel = Channel5

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<UART8>

type Instance = DMA1

type Stream = Stream6<DMA1>

type Channel = Channel5

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<USART1>

type Instance = DMA2

type Stream = Stream2<DMA2>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<USART2>

type Instance = DMA1

type Stream = Stream5<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<USART3>

type Instance = DMA1

type Stream = Stream1<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Rx<USART6>

type Instance = DMA2

type Stream = Stream1<DMA2>

type Channel = Channel5

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<UART4>

type Instance = DMA1

type Stream = Stream4<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<UART5>

type Instance = DMA1

type Stream = Stream7<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<UART7>

type Instance = DMA1

type Stream = Stream1<DMA1>

type Channel = Channel5

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<UART8>

type Instance = DMA1

type Stream = Stream0<DMA1>

type Channel = Channel5

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<USART1>

type Instance = DMA2

type Stream = Stream7<DMA2>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<USART2>

type Instance = DMA1

type Stream = Stream6<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<USART3>

type Instance = DMA1

type Stream = Stream3<DMA1>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::serial::Tx<USART6>

type Instance = DMA2

type Stream = Stream6<DMA2>

type Channel = Channel5

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Rx<SPI1>

type Instance = DMA2

type Stream = Stream0<DMA2>

type Channel = Channel3

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Rx<SPI2>

type Instance = DMA1

type Stream = Stream3<DMA1>

type Channel = Channel0

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Rx<SPI3>

type Instance = DMA1

type Stream = Stream0<DMA1>

type Channel = Channel0

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Rx<SPI4>

type Instance = DMA2

type Stream = Stream0<DMA2>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Rx<SPI5>

type Instance = DMA2

type Stream = Stream3<DMA2>

type Channel = Channel2

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Rx<SPI6>

type Instance = DMA2

type Stream = Stream6<DMA2>

type Channel = Channel1

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Tx<SPI1>

type Instance = DMA2

type Stream = Stream3<DMA2>

type Channel = Channel3

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Tx<SPI2>

type Instance = DMA1

type Stream = Stream4<DMA1>

type Channel = Channel0

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Tx<SPI3>

type Instance = DMA1

type Stream = Stream5<DMA1>

type Channel = Channel0

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Tx<SPI4>

type Instance = DMA2

type Stream = Stream1<DMA2>

type Channel = Channel4

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Tx<SPI5>

type Instance = DMA2

type Stream = Stream4<DMA2>

type Channel = Channel2

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const INTERRUPT: Interrupt

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impl Target for stm32f7xx_hal::spi::Tx<SPI6>

type Instance = DMA2

type Stream = Stream5<DMA2>

type Channel = Channel1

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