[−][src]Struct stm32f4xx_hal::stm32::rcc::RegisterBlock

#[repr(C)]

pub struct RegisterBlock {
    pub cr: CR,
    pub pllcfgr: PLLCFGR,
    pub cfgr: CFGR,
    pub cir: CIR,
    pub ahb1rstr: AHB1RSTR,
    pub ahb2rstr: AHB2RSTR,
    pub ahb3rstr: AHB3RSTR,
    pub apb1rstr: APB1RSTR,
    pub apb2rstr: APB2RSTR,
    pub ahb1enr: AHB1ENR,
    pub ahb2enr: AHB2ENR,
    pub ahb3enr: AHB3ENR,
    pub apb1enr: APB1ENR,
    pub apb2enr: APB2ENR,
    pub ahb1lpenr: AHB1LPENR,
    pub ahb2lpenr: AHB2LPENR,
    pub ahb3lpenr: AHB3LPENR,
    pub apb1lpenr: APB1LPENR,
    pub apb2lpenr: APB2LPENR,
    pub bdcr: BDCR,
    pub csr: CSR,
    pub sscgr: SSCGR,
    pub plli2scfgr: PLLI2SCFGR,
    pub pllsaicfgr: PLLSAICFGR,
    pub dckcfgr: DCKCFGR,
    // some fields omitted
}

Register block

Fields

cr: CR

0x00 - clock control register

pllcfgr: PLLCFGR

0x04 - PLL configuration register

cfgr: CFGR

0x08 - clock configuration register

cir: CIR

0x0c - clock interrupt register

ahb1rstr: AHB1RSTR

0x10 - AHB1 peripheral reset register

ahb2rstr: AHB2RSTR

0x14 - AHB2 peripheral reset register

ahb3rstr: AHB3RSTR

0x18 - AHB3 peripheral reset register

apb1rstr: APB1RSTR

0x20 - APB1 peripheral reset register

apb2rstr: APB2RSTR

0x24 - APB2 peripheral reset register

ahb1enr: AHB1ENR

0x30 - AHB1 peripheral clock register

ahb2enr: AHB2ENR

0x34 - AHB2 peripheral clock enable register

ahb3enr: AHB3ENR

0x38 - AHB3 peripheral clock enable register

apb1enr: APB1ENR

0x40 - APB1 peripheral clock enable register

apb2enr: APB2ENR

0x44 - APB2 peripheral clock enable register

ahb1lpenr: AHB1LPENR

0x50 - AHB1 peripheral clock enable in low power mode register

ahb2lpenr: AHB2LPENR

0x54 - AHB2 peripheral clock enable in low power mode register

ahb3lpenr: AHB3LPENR

0x58 - AHB3 peripheral clock enable in low power mode register

apb1lpenr: APB1LPENR

0x60 - APB1 peripheral clock enable in low power mode register

apb2lpenr: APB2LPENR

0x64 - APB2 peripheral clock enabled in low power mode register

bdcr: BDCR

0x70 - Backup domain control register

csr: CSR

0x74 - clock control & status register

sscgr: SSCGR

0x80 - spread spectrum clock generation register

plli2scfgr: PLLI2SCFGR

0x84 - PLLI2S configuration register

pllsaicfgr: PLLSAICFGR

0x88 - RCC PLL configuration register

dckcfgr: DCKCFGR

0x8c - RCC Dedicated Clock Configuration Register

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