Struct stm32f4xx_hal::timer::pwm_input::PwmInput

pub struct PwmInput<TIM, PINS> where
    TIM: Instance + WithPwm,
    PINS: Pins<TIM>,  { /* private fields */ }

Represents a TIMer configured as a PWM input. This peripheral will emit an interrupt on CC2 events, which occurs at two times in this mode:

1. When a new cycle is started: the duty cycle will be 1.00
2. When the period is captured. the duty cycle will be an observable value. An example interrupt handler is provided:

use stm32f4xx_hal::pac::TIM8;
use stm32f4xx_hal::timer::Timer;
use stm32f4xx_hal::pwm_input::PwmInput;
use stm32f4xx_hal::gpio::gpioc::PC6;
use stm32f4xx_hal::gpio::Alternate;

type Monitor = PwmInput<TIM8, PC6<Alternate<3>>>;

fn tim8_cc2(monitor: &Monitor) {
            let duty_clocks = monitor.get_duty_cycle_clocks();
            let period_clocks = monitor.get_period_clocks();
            // check if this interrupt was caused by a capture at the wrong CC2,
            // peripheral limitation.
            if !monitor.is_valid_capture(){
                return;
            }
            let duty = monitor.get_duty_cycle();
}

Implementations

impl<TIM, PINS> PwmInput<TIM, PINS> where
    TIM: Instance + WithPwm,
    PINS: Pins<TIM>, 

pub fn release(self) -> Timer<TIM>

impl<PINS> PwmInput<TIM2, PINS> where
    PINS: Pins<TIM2>, 

pub fn get_period_clocks(&self) -> <TIM2 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM2 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM3, PINS> where
    PINS: Pins<TIM3>, 

pub fn get_period_clocks(&self) -> <TIM3 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM3 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM4, PINS> where
    PINS: Pins<TIM4>, 

pub fn get_period_clocks(&self) -> <TIM4 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM4 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM8, PINS> where
    PINS: Pins<TIM8>, 

pub fn get_period_clocks(&self) -> <TIM8 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM8 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM12, PINS> where
    PINS: Pins<TIM12>, 

pub fn get_period_clocks(&self) -> <TIM12 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM12 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM1, PINS> where
    PINS: Pins<TIM1>, 

pub fn get_period_clocks(&self) -> <TIM1 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM1 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM5, PINS> where
    PINS: Pins<TIM5>, 

pub fn get_period_clocks(&self) -> <TIM5 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM5 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

impl<PINS> PwmInput<TIM9, PINS> where
    PINS: Pins<TIM9>, 

pub fn get_period_clocks(&self) -> <TIM9 as General>::Width

Period of PWM signal in terms of clock cycles

pub fn get_duty_cycle_clocks(&self) -> <TIM9 as General>::Width

Duty cycle in terms of clock cycles

pub fn get_duty_cycle(&self) -> f32

Observed duty cycle as a float in range [0.00, 1.00]

pub fn is_valid_capture(&self) -> bool

Returns whether the timer’s duty cycle is a valid observation (Limitation of how the captures work is extra CC2 interrupts are generated when the PWM cycle enters a new period).

Methods from Deref<Target = Timer<TIM>>

pub fn configure(&mut self, clocks: &Clocks)

pub fn configure_external(&mut self, clocks: &Clocks)

pub fn listen(&mut self, event: SysEvent)

Starts listening for an event

pub fn unlisten(&mut self, event: SysEvent)

Stops listening for an event

pub fn configure(&mut self, clocks: &Clocks)

pub fn listen(&mut self, event: Event)

Starts listening for an event

Note, you will also have to enable the TIM2 interrupt in the NVIC to start receiving events.

pub fn clear_interrupt(&mut self, event: Event)

Clears interrupt associated with event.

If the interrupt is not cleared, it will immediately retrigger after the ISR has finished.

pub fn unlisten(&mut self, event: Event)

Stops listening for an event

pub fn set_master_mode(&mut self, mode: TIM::Mms)

Trait Implementations

impl<TIM, PINS> Deref for PwmInput<TIM, PINS> where
    TIM: Instance + WithPwm,
    PINS: Pins<TIM>, 

type Target = Timer<TIM>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl<TIM, PINS> DerefMut for PwmInput<TIM, PINS> where
    TIM: Instance + WithPwm,
    PINS: Pins<TIM>, 

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.