Trait stm32f4xx_hal::rng::RngExt

source · [−]

pub trait RngExt {
    fn constrain(self, clocks: &Clocks) -> Rng;
}

Expand description

Helper trait to implement the constrain method for the RNG peripheral which is how the Rng struct is created.

Usage:

let dp = pac::Peripherals::take().unwrap();
let rcc = dp.RCC.constrain();
let clocks = rcc.cfgr.require_pll48clk().freeze();
let mut rand_source = dp.RNG.constrain(clocks);

Required Methods

source

fn constrain(self, clocks: &Clocks) -> Rng

Enables the hardware random generator and provides the Rng struct.

The datasheet states, that the RNG_CLK must not be less than 1/16 HCLK (HCLK is the CPU clock), otherwise all reads of the RNG would return a ClockError (CECS error). As the RNG_CLK always seems to be connected to the PLL48_CLK and the maximum value of HCLK is 168MHz, this is always true as long as the PLL48_CLK is enabled. This can be done with the require_pll48clk function.

See reference manual section 24.4.2 for more details

Panics

This function will panic if PLL48_CLK < 1/16 HCLK.