Struct stm32f429x::otg_hs_host::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub otg_hs_hcfg: OtgHsHcfg, pub otg_hs_hfir: OtgHsHfir, pub otg_hs_hfnum: OtgHsHfnum, pub otg_hs_hptxsts: OtgHsHptxsts, pub otg_hs_haint: OtgHsHaint, pub otg_hs_haintmsk: OtgHsHaintmsk, pub otg_hs_hprt: OtgHsHprt, pub otg_hs_hcchar0: OtgHsHcchar0, pub otg_hs_hcsplt0: OtgHsHcsplt0, pub otg_hs_hcint0: OtgHsHcint0, pub otg_hs_hcintmsk0: OtgHsHcintmsk0, pub otg_hs_hctsiz0: OtgHsHctsiz0, pub otg_hs_hcdma0: OtgHsHcdma0, pub otg_hs_hcchar1: OtgHsHcchar1, pub otg_hs_hcsplt1: OtgHsHcsplt1, pub otg_hs_hcint1: OtgHsHcint1, pub otg_hs_hcintmsk1: OtgHsHcintmsk1, pub otg_hs_hctsiz1: OtgHsHctsiz1, pub otg_hs_hcdma1: OtgHsHcdma1, pub otg_hs_hcchar2: OtgHsHcchar2, pub otg_hs_hcsplt2: OtgHsHcsplt2, pub otg_hs_hcint2: OtgHsHcint2, pub otg_hs_hcintmsk2: OtgHsHcintmsk2, pub otg_hs_hctsiz2: OtgHsHctsiz2, pub otg_hs_hcdma2: OtgHsHcdma2, pub otg_hs_hcchar3: OtgHsHcchar3, pub otg_hs_hcsplt3: OtgHsHcsplt3, pub otg_hs_hcint3: OtgHsHcint3, pub otg_hs_hcintmsk3: OtgHsHcintmsk3, pub otg_hs_hctsiz3: OtgHsHctsiz3, pub otg_hs_hcdma3: OtgHsHcdma3, pub otg_hs_hcchar4: OtgHsHcchar4, pub otg_hs_hcsplt4: OtgHsHcsplt4, pub otg_hs_hcint4: OtgHsHcint4, pub otg_hs_hcintmsk4: OtgHsHcintmsk4, pub otg_hs_hctsiz4: OtgHsHctsiz4, pub otg_hs_hcdma4: OtgHsHcdma4, pub otg_hs_hcchar5: OtgHsHcchar5, pub otg_hs_hcsplt5: OtgHsHcsplt5, pub otg_hs_hcint5: OtgHsHcint5, pub otg_hs_hcintmsk5: OtgHsHcintmsk5, pub otg_hs_hctsiz5: OtgHsHctsiz5, pub otg_hs_hcdma5: OtgHsHcdma5, pub otg_hs_hcchar6: OtgHsHcchar6, pub otg_hs_hcsplt6: OtgHsHcsplt6, pub otg_hs_hcint6: OtgHsHcint6, pub otg_hs_hcintmsk6: OtgHsHcintmsk6, pub otg_hs_hctsiz6: OtgHsHctsiz6, pub otg_hs_hcdma6: OtgHsHcdma6, pub otg_hs_hcchar7: OtgHsHcchar7, pub otg_hs_hcsplt7: OtgHsHcsplt7, pub otg_hs_hcint7: OtgHsHcint7, pub otg_hs_hcintmsk7: OtgHsHcintmsk7, pub otg_hs_hctsiz7: OtgHsHctsiz7, pub otg_hs_hcdma7: OtgHsHcdma7, pub otg_hs_hcchar8: OtgHsHcchar8, pub otg_hs_hcsplt8: OtgHsHcsplt8, pub otg_hs_hcint8: OtgHsHcint8, pub otg_hs_hcintmsk8: OtgHsHcintmsk8, pub otg_hs_hctsiz8: OtgHsHctsiz8, pub otg_hs_hcdma8: OtgHsHcdma8, pub otg_hs_hcchar9: OtgHsHcchar9, pub otg_hs_hcsplt9: OtgHsHcsplt9, pub otg_hs_hcint9: OtgHsHcint9, pub otg_hs_hcintmsk9: OtgHsHcintmsk9, pub otg_hs_hctsiz9: OtgHsHctsiz9, pub otg_hs_hcdma9: OtgHsHcdma9, pub otg_hs_hcchar10: OtgHsHcchar10, pub otg_hs_hcsplt10: OtgHsHcsplt10, pub otg_hs_hcint10: OtgHsHcint10, pub otg_hs_hcintmsk10: OtgHsHcintmsk10, pub otg_hs_hctsiz10: OtgHsHctsiz10, pub otg_hs_hcdma10: OtgHsHcdma10, pub otg_hs_hcchar11: OtgHsHcchar11, pub otg_hs_hcsplt11: OtgHsHcsplt11, pub otg_hs_hcint11: OtgHsHcint11, pub otg_hs_hcintmsk11: OtgHsHcintmsk11, pub otg_hs_hctsiz11: OtgHsHctsiz11, pub otg_hs_hcdma11: OtgHsHcdma11, // some fields omitted }
Register block
Fields
otg_hs_hcfg: OtgHsHcfg
0x00 - OTG_HS host configuration register
otg_hs_hfir: OtgHsHfir
0x04 - OTG_HS Host frame interval register
otg_hs_hfnum: OtgHsHfnum
0x08 - OTG_HS host frame number/frame time remaining register
otg_hs_hptxsts: OtgHsHptxsts
0x10 - OTG_HS_Host periodic transmit FIFO/queue status register
otg_hs_haint: OtgHsHaint
0x14 - OTG_HS Host all channels interrupt register
otg_hs_haintmsk: OtgHsHaintmsk
0x18 - OTG_HS host all channels interrupt mask register
otg_hs_hprt: OtgHsHprt
0x40 - OTG_HS host port control and status register
otg_hs_hcchar0: OtgHsHcchar0
0x100 - OTG_HS host channel-0 characteristics register
otg_hs_hcsplt0: OtgHsHcsplt0
0x104 - OTG_HS host channel-0 split control register
otg_hs_hcint0: OtgHsHcint0
0x108 - OTG_HS host channel-11 interrupt register
otg_hs_hcintmsk0: OtgHsHcintmsk0
0x10c - OTG_HS host channel-11 interrupt mask register
otg_hs_hctsiz0: OtgHsHctsiz0
0x110 - OTG_HS host channel-11 transfer size register
otg_hs_hcdma0: OtgHsHcdma0
0x114 - OTG_HS host channel-0 DMA address register
otg_hs_hcchar1: OtgHsHcchar1
0x120 - OTG_HS host channel-1 characteristics register
otg_hs_hcsplt1: OtgHsHcsplt1
0x124 - OTG_HS host channel-1 split control register
otg_hs_hcint1: OtgHsHcint1
0x128 - OTG_HS host channel-1 interrupt register
otg_hs_hcintmsk1: OtgHsHcintmsk1
0x12c - OTG_HS host channel-1 interrupt mask register
otg_hs_hctsiz1: OtgHsHctsiz1
0x130 - OTG_HS host channel-1 transfer size register
otg_hs_hcdma1: OtgHsHcdma1
0x134 - OTG_HS host channel-1 DMA address register
otg_hs_hcchar2: OtgHsHcchar2
0x140 - OTG_HS host channel-2 characteristics register
otg_hs_hcsplt2: OtgHsHcsplt2
0x144 - OTG_HS host channel-2 split control register
otg_hs_hcint2: OtgHsHcint2
0x148 - OTG_HS host channel-2 interrupt register
otg_hs_hcintmsk2: OtgHsHcintmsk2
0x14c - OTG_HS host channel-2 interrupt mask register
otg_hs_hctsiz2: OtgHsHctsiz2
0x150 - OTG_HS host channel-2 transfer size register
otg_hs_hcdma2: OtgHsHcdma2
0x154 - OTG_HS host channel-2 DMA address register
otg_hs_hcchar3: OtgHsHcchar3
0x160 - OTG_HS host channel-3 characteristics register
otg_hs_hcsplt3: OtgHsHcsplt3
0x164 - OTG_HS host channel-3 split control register
otg_hs_hcint3: OtgHsHcint3
0x168 - OTG_HS host channel-3 interrupt register
otg_hs_hcintmsk3: OtgHsHcintmsk3
0x16c - OTG_HS host channel-3 interrupt mask register
otg_hs_hctsiz3: OtgHsHctsiz3
0x170 - OTG_HS host channel-3 transfer size register
otg_hs_hcdma3: OtgHsHcdma3
0x174 - OTG_HS host channel-3 DMA address register
otg_hs_hcchar4: OtgHsHcchar4
0x180 - OTG_HS host channel-4 characteristics register
otg_hs_hcsplt4: OtgHsHcsplt4
0x184 - OTG_HS host channel-4 split control register
otg_hs_hcint4: OtgHsHcint4
0x188 - OTG_HS host channel-4 interrupt register
otg_hs_hcintmsk4: OtgHsHcintmsk4
0x18c - OTG_HS host channel-4 interrupt mask register
otg_hs_hctsiz4: OtgHsHctsiz4
0x190 - OTG_HS host channel-4 transfer size register
otg_hs_hcdma4: OtgHsHcdma4
0x194 - OTG_HS host channel-4 DMA address register
otg_hs_hcchar5: OtgHsHcchar5
0x1a0 - OTG_HS host channel-5 characteristics register
otg_hs_hcsplt5: OtgHsHcsplt5
0x1a4 - OTG_HS host channel-5 split control register
otg_hs_hcint5: OtgHsHcint5
0x1a8 - OTG_HS host channel-5 interrupt register
otg_hs_hcintmsk5: OtgHsHcintmsk5
0x1ac - OTG_HS host channel-5 interrupt mask register
otg_hs_hctsiz5: OtgHsHctsiz5
0x1b0 - OTG_HS host channel-5 transfer size register
otg_hs_hcdma5: OtgHsHcdma5
0x1b4 - OTG_HS host channel-5 DMA address register
otg_hs_hcchar6: OtgHsHcchar6
0x1c0 - OTG_HS host channel-6 characteristics register
otg_hs_hcsplt6: OtgHsHcsplt6
0x1c4 - OTG_HS host channel-6 split control register
otg_hs_hcint6: OtgHsHcint6
0x1c8 - OTG_HS host channel-6 interrupt register
otg_hs_hcintmsk6: OtgHsHcintmsk6
0x1cc - OTG_HS host channel-6 interrupt mask register
otg_hs_hctsiz6: OtgHsHctsiz6
0x1d0 - OTG_HS host channel-6 transfer size register
otg_hs_hcdma6: OtgHsHcdma6
0x1d4 - OTG_HS host channel-6 DMA address register
otg_hs_hcchar7: OtgHsHcchar7
0x1e0 - OTG_HS host channel-7 characteristics register
otg_hs_hcsplt7: OtgHsHcsplt7
0x1e4 - OTG_HS host channel-7 split control register
otg_hs_hcint7: OtgHsHcint7
0x1e8 - OTG_HS host channel-7 interrupt register
otg_hs_hcintmsk7: OtgHsHcintmsk7
0x1ec - OTG_HS host channel-7 interrupt mask register
otg_hs_hctsiz7: OtgHsHctsiz7
0x1f0 - OTG_HS host channel-7 transfer size register
otg_hs_hcdma7: OtgHsHcdma7
0x1f4 - OTG_HS host channel-7 DMA address register
otg_hs_hcchar8: OtgHsHcchar8
0x200 - OTG_HS host channel-8 characteristics register
otg_hs_hcsplt8: OtgHsHcsplt8
0x204 - OTG_HS host channel-8 split control register
otg_hs_hcint8: OtgHsHcint8
0x208 - OTG_HS host channel-8 interrupt register
otg_hs_hcintmsk8: OtgHsHcintmsk8
0x20c - OTG_HS host channel-8 interrupt mask register
otg_hs_hctsiz8: OtgHsHctsiz8
0x210 - OTG_HS host channel-8 transfer size register
otg_hs_hcdma8: OtgHsHcdma8
0x214 - OTG_HS host channel-8 DMA address register
otg_hs_hcchar9: OtgHsHcchar9
0x220 - OTG_HS host channel-9 characteristics register
otg_hs_hcsplt9: OtgHsHcsplt9
0x224 - OTG_HS host channel-9 split control register
otg_hs_hcint9: OtgHsHcint9
0x228 - OTG_HS host channel-9 interrupt register
otg_hs_hcintmsk9: OtgHsHcintmsk9
0x22c - OTG_HS host channel-9 interrupt mask register
otg_hs_hctsiz9: OtgHsHctsiz9
0x230 - OTG_HS host channel-9 transfer size register
otg_hs_hcdma9: OtgHsHcdma9
0x234 - OTG_HS host channel-9 DMA address register
otg_hs_hcchar10: OtgHsHcchar10
0x240 - OTG_HS host channel-10 characteristics register
otg_hs_hcsplt10: OtgHsHcsplt10
0x244 - OTG_HS host channel-10 split control register
otg_hs_hcint10: OtgHsHcint10
0x248 - OTG_HS host channel-10 interrupt register
otg_hs_hcintmsk10: OtgHsHcintmsk10
0x24c - OTG_HS host channel-10 interrupt mask register
otg_hs_hctsiz10: OtgHsHctsiz10
0x250 - OTG_HS host channel-10 transfer size register
otg_hs_hcdma10: OtgHsHcdma10
0x254 - OTG_HS host channel-10 DMA address register
otg_hs_hcchar11: OtgHsHcchar11
0x260 - OTG_HS host channel-11 characteristics register
otg_hs_hcsplt11: OtgHsHcsplt11
0x264 - OTG_HS host channel-11 split control register
otg_hs_hcint11: OtgHsHcint11
0x268 - OTG_HS host channel-11 interrupt register
otg_hs_hcintmsk11: OtgHsHcintmsk11
0x26c - OTG_HS host channel-11 interrupt mask register
otg_hs_hctsiz11: OtgHsHctsiz11
0x270 - OTG_HS host channel-11 transfer size register
otg_hs_hcdma11: OtgHsHcdma11
0x274 - OTG_HS host channel-11 DMA address register