Struct stm32f3xx_hal_v2::rcc::CFGR

pub struct CFGR { /* fields omitted */ }

Clock configuration

An instance of this struct is acquired from the RCC struct.

let dp = pac::Peripherals::take().unwrap();
let rcc = dp.RCC.constrain();
use_cfgr(&mut rcc.cfgr)

Implementations

impl CFGR

pub fn use_hse<F>(self, freq: F) -> Self where
    F: Into<Hertz>, 

Uses HSE (external oscillator) instead of HSI (internal RC oscillator) as the clock source.

Will result in a hang if an external oscillator is not connected or it fails to start, unless css is enabled.

pub fn bypass_hse(self) -> Self

Enable HSE bypass.

Uses user provided clock signal instead of an external oscillator. OSC_OUT pin is free and can be used as GPIO.

No effect if HSE is not enabled.

pub fn enable_css(self) -> Self

Enable CSS (Clock Security System).

System clock is automatically switched to HSI and an interrupt (CSSI) is generated when HSE clock failure is detected.

No effect if HSE is not enabled.

pub fn hclk<F>(self, freq: F) -> Self where
    F: Into<Hertz>, 

Sets a frequency for the AHB bus

pub fn pclk1<F>(self, freq: F) -> Self where
    F: Into<Hertz>, 

Sets a frequency for the APB1 bus

• Maximal supported frequency: 36 Mhz

If not manually set, it will be set to CFGR::sysclk frequency or CFGR::sysclk frequency / 2, if CFGR::sysclk > 36 Mhz

pub fn pclk2<F>(self, freq: F) -> Self where
    F: Into<Hertz>, 

Sets a frequency for the APB2 bus

Resolution and Limits

• Maximal supported frequency with HSE: 72 Mhz
• Maximal supported frequency without HSE: 64 Mhz

This is true for devices except the following devices, as these allow finer resolutions even when using the internal oscillator:

[stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]

pub fn sysclk<F>(self, freq: F) -> Self where
    F: Into<Hertz>, 

Sets the system (core) frequency

Resolution and Limits

• Maximal supported frequency with HSE: 72 Mhz
• Maximal supported frequency without HSE: 64 Mhz

If CFGR::hse is not used, therefor HSI / 2 is used. Only multiples of (HSI / 2) (4 Mhz) are allowed.

This is true for devices except the following devices, as these allow finer resolutions even when using the internal oscillator:

[stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]

pub fn freeze(self, acr: &mut ACR) -> Clocks

Freezes the clock configuration, making it effective

This function internally calculates the specific. divisors for the different clock peripheries.

Panics

If any of the set frequencies via sysclk, hclk, pclk1 or pclk2 are invalid or can not be reached because of e.g. to low frequencies of the former, as sysclk depends on the configuration of hclk this function will panic.

Trait Implementations

impl Default for CFGR

pub fn default() -> CFGR

Returns the "default value" for a type.