Struct stm32f334::hrtim_common::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub cr1: CR1, pub cr2: CR2, pub isr: ISR, pub icr: ICR, pub ier: IER, pub oenr: OENR, pub disr: DISR, pub odsr: ODSR, pub bmcr: BMCR, pub bmtrg: BMTRG, pub bmcmpr6: BMCMPR6, pub bmper: BMPER, pub eecr1: EECR1, pub eecr2: EECR2, pub eecr3: EECR3, pub adc1r: ADC1R, pub adc2r: ADC2R, pub adc3r: ADC3R, pub adc4r: ADC4R, pub dllcr: DLLCR, pub fltinr1: FLTINR1, pub fltinr2: FLTINR2, pub bdmupdr: BDMUPDR, pub bdtx_upr: BDTXUPR, pub bdmadr: BDMADR, }
Register block
Fields
cr1: CR1
0x00 - Control Register 1
cr2: CR2
0x04 - Control Register 2
isr: ISR
0x08 - Interrupt Status Register
icr: ICR
0x0c - Interrupt Clear Register
ier: IER
0x10 - Interrupt Enable Register
oenr: OENR
0x14 - Output Enable Register
disr: DISR
0x18 - DISR
odsr: ODSR
0x1c - Output Disable Status Register
bmcr: BMCR
0x20 - Burst Mode Control Register
bmtrg: BMTRG
0x24 - BMTRG
bmcmpr6: BMCMPR6
0x28 - BMCMPR6
bmper: BMPER
0x2c - Burst Mode Period Register
eecr1: EECR1
0x30 - Timer External Event Control Register 1
eecr2: EECR2
0x34 - Timer External Event Control Register 2
eecr3: EECR3
0x38 - Timer External Event Control Register 3
adc1r: ADC1R
0x3c - ADC Trigger 1 Register
adc2r: ADC2R
0x40 - ADC Trigger 2 Register
adc3r: ADC3R
0x44 - ADC Trigger 3 Register
adc4r: ADC4R
0x48 - ADC Trigger 4 Register
dllcr: DLLCR
0x4c - DLL Control Register
fltinr1: FLTINR1
0x50 - HRTIM Fault Input Register 1
fltinr2: FLTINR2
0x54 - HRTIM Fault Input Register 2
bdmupdr: BDMUPDR
0x58 - BDMUPDR
bdtx_upr: BDTXUPR
0x5c - Burst DMA Timerx update Register
bdmadr: BDMADR
0x60 - Burst DMA Data Register