Struct stm32f334::hrtim_master::mcr::W
[−]
[src]
pub struct W { /* fields omitted */ }Value to write to the register
Methods
impl W[src]
pub fn reset_value() -> W[src]
Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self[src]
Writes raw bits to the register
pub fn brstdma(&mut self) -> _BRSTDMAW[src]
Bits 30:31 - Burst DMA Update
pub fn mrepu(&mut self) -> _MREPUW[src]
Bit 29 - Master Timer Repetition update
pub fn preen(&mut self) -> _PREENW[src]
Bit 27 - Preload enable
pub fn dacsync(&mut self) -> _DACSYNCW[src]
Bits 25:26 - DAC Synchronization
pub fn tecen(&mut self) -> _TECENW[src]
Bit 21 - Timer E counter enable
pub fn tdcen(&mut self) -> _TDCENW[src]
Bit 20 - Timer D counter enable
pub fn tccen(&mut self) -> _TCCENW[src]
Bit 19 - Timer C counter enable
pub fn tbcen(&mut self) -> _TBCENW[src]
Bit 18 - Timer B counter enable
pub fn tacen(&mut self) -> _TACENW[src]
Bit 17 - Timer A counter enable
pub fn mcen(&mut self) -> _MCENW[src]
Bit 16 - Master Counter enable
pub fn sync_src(&mut self) -> _SYNC_SRCW[src]
Bits 14:15 - Synchronization source
pub fn syncout(&mut self) -> _SYNCOUTW[src]
Bits 12:13 - Synchronization output
pub fn syncstrtm(&mut self) -> _SYNCSTRTMW[src]
Bit 11 - Synchronization Starts Master
pub fn syncrstm(&mut self) -> _SYNCRSTMW[src]
Bit 10 - Synchronization Resets Master
pub fn syncin(&mut self) -> _SYNCINW[src]
Bits 8:9 - ynchronization input
pub fn half(&mut self) -> _HALFW[src]
Bit 5 - Half mode enable
pub fn retrig(&mut self) -> _RETRIGW[src]
Bit 4 - Master Re-triggerable mode
pub fn cont(&mut self) -> _CONTW[src]
Bit 3 - Master Continuous mode
pub fn ckpsc(&mut self) -> _CKPSCW[src]
Bits 0:2 - HRTIM Master Clock prescaler