Struct stm32f334::hrtim_master::mcr::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn brstdma(&self) -> BRSTDMAR[src]
Bits 30:31 - Burst DMA Update
pub fn mrepu(&self) -> MREPUR[src]
Bit 29 - Master Timer Repetition update
pub fn preen(&self) -> PREENR[src]
Bit 27 - Preload enable
pub fn dacsync(&self) -> DACSYNCR[src]
Bits 25:26 - DAC Synchronization
pub fn tecen(&self) -> TECENR[src]
Bit 21 - Timer E counter enable
pub fn tdcen(&self) -> TDCENR[src]
Bit 20 - Timer D counter enable
pub fn tccen(&self) -> TCCENR[src]
Bit 19 - Timer C counter enable
pub fn tbcen(&self) -> TBCENR[src]
Bit 18 - Timer B counter enable
pub fn tacen(&self) -> TACENR[src]
Bit 17 - Timer A counter enable
pub fn mcen(&self) -> MCENR[src]
Bit 16 - Master Counter enable
pub fn sync_src(&self) -> SYNC_SRCR[src]
Bits 14:15 - Synchronization source
pub fn syncout(&self) -> SYNCOUTR[src]
Bits 12:13 - Synchronization output
pub fn syncstrtm(&self) -> SYNCSTRTMR[src]
Bit 11 - Synchronization Starts Master
pub fn syncrstm(&self) -> SYNCRSTMR[src]
Bit 10 - Synchronization Resets Master
pub fn syncin(&self) -> SYNCINR[src]
Bits 8:9 - ynchronization input
pub fn half(&self) -> HALFR[src]
Bit 5 - Half mode enable
pub fn retrig(&self) -> RETRIGR[src]
Bit 4 - Master Re-triggerable mode
pub fn cont(&self) -> CONTR[src]
Bit 3 - Master Continuous mode
pub fn ckpsc(&self) -> CKPSCR[src]
Bits 0:2 - HRTIM Master Clock prescaler