Struct stm32f334::can::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub mcr: MCR,
    pub msr: MSR,
    pub tsr: TSR,
    pub rf0r: RF0R,
    pub rf1r: RF1R,
    pub ier: IER,
    pub esr: ESR,
    pub btr: BTR,
    pub ti0r: TI0R,
    pub tdt0r: TDT0R,
    pub tdl0r: TDL0R,
    pub tdh0r: TDH0R,
    pub ti1r: TI1R,
    pub tdt1r: TDT1R,
    pub tdl1r: TDL1R,
    pub tdh1r: TDH1R,
    pub ti2r: TI2R,
    pub tdt2r: TDT2R,
    pub tdl2r: TDL2R,
    pub tdh2r: TDH2R,
    pub ri0r: RI0R,
    pub rdt0r: RDT0R,
    pub rdl0r: RDL0R,
    pub rdh0r: RDH0R,
    pub ri1r: RI1R,
    pub rdt1r: RDT1R,
    pub rdl1r: RDL1R,
    pub rdh1r: RDH1R,
    pub fmr: FMR,
    pub fm1r: FM1R,
    pub fs1r: FS1R,
    pub ffa1r: FFA1R,
    pub fa1r: FA1R,
    pub f0r1: F0R1,
    pub f0r2: F0R2,
    pub f1r1: F1R1,
    pub f1r2: F1R2,
    pub f27r1: F27R1,
    pub f27r2: F27R2,
    // some fields omitted
}

Register block

Fields

mcr: MCR

0x00 - master control register

msr: MSR

0x04 - master status register

tsr: TSR

0x08 - transmit status register

rf0r: RF0R

0x0c - receive FIFO 0 register

rf1r: RF1R

0x10 - receive FIFO 1 register

ier: IER

0x14 - interrupt enable register

esr: ESR

0x18 - error status register

btr: BTR

0x1c - bit timing register

ti0r: TI0R

0x180 - TX mailbox identifier register

tdt0r: TDT0R

0x184 - mailbox data length control and time stamp register

tdl0r: TDL0R

0x188 - mailbox data low register

tdh0r: TDH0R

0x18c - mailbox data high register

ti1r: TI1R

0x190 - TX mailbox identifier register

tdt1r: TDT1R

0x194 - mailbox data length control and time stamp register

tdl1r: TDL1R

0x198 - mailbox data low register

tdh1r: TDH1R

0x19c - mailbox data high register

ti2r: TI2R

0x1a0 - TX mailbox identifier register

tdt2r: TDT2R

0x1a4 - mailbox data length control and time stamp register

tdl2r: TDL2R

0x1a8 - mailbox data low register

tdh2r: TDH2R

0x1ac - mailbox data high register

ri0r: RI0R

0x1b0 - receive FIFO mailbox identifier register

rdt0r: RDT0R

0x1b4 - receive FIFO mailbox data length control and time stamp register

rdl0r: RDL0R

0x1b8 - receive FIFO mailbox data low register

rdh0r: RDH0R

0x1bc - receive FIFO mailbox data high register

ri1r: RI1R

0x1c0 - receive FIFO mailbox identifier register

rdt1r: RDT1R

0x1c4 - receive FIFO mailbox data length control and time stamp register

rdl1r: RDL1R

0x1c8 - receive FIFO mailbox data low register

rdh1r: RDH1R

0x1cc - receive FIFO mailbox data high register

fmr: FMR

0x200 - filter master register

fm1r: FM1R

0x204 - filter mode register

fs1r: FS1R

0x20c - filter scale register

ffa1r: FFA1R

0x214 - filter FIFO assignment register

fa1r: FA1R

0x21c - CAN filter activation register

f0r1: F0R1

0x240 - Filter bank 0 register 1

f0r2: F0R2

0x244 - Filter bank 0 register 2

f1r1: F1R1

0x248 - Filter bank 1 register 1

f1r2: F1R2

0x24c - Filter bank 1 register 2

f27r1: F27R1

0x318 - Filter bank 27 register 1

f27r2: F27R2

0x31c - Filter bank 27 register 2

Trait Implementations