Struct stm32f1xx_hal::pac::ethernet_mmc::RegisterBlock

source · 
pub struct RegisterBlock {
    pub mmccr: Reg<MMCCR_SPEC>,
    pub mmcrir: Reg<MMCRIR_SPEC>,
    pub mmctir: Reg<MMCTIR_SPEC>,
    pub mmcrimr: Reg<MMCRIMR_SPEC>,
    pub mmctimr: Reg<MMCTIMR_SPEC>,
    pub mmctgfsccr: Reg<MMCTGFSCCR_SPEC>,
    pub mmctgfmsccr: Reg<MMCTGFMSCCR_SPEC>,
    pub mmctgfcr: Reg<MMCTGFCR_SPEC>,
    pub mmcrfcecr: Reg<MMCRFCECR_SPEC>,
    pub mmcrfaecr: Reg<MMCRFAECR_SPEC>,
    pub mmcrgufcr: Reg<MMCRGUFCR_SPEC>,
    /* private fields */
}
Expand description

Register block

Fields§

§mmccr: Reg<MMCCR_SPEC>

0x00 - Ethernet MMC control register (ETH_MMCCR)

§mmcrir: Reg<MMCRIR_SPEC>

0x04 - Ethernet MMC receive interrupt register (ETH_MMCRIR)

§mmctir: Reg<MMCTIR_SPEC>

0x08 - Ethernet MMC transmit interrupt register (ETH_MMCTIR)

§mmcrimr: Reg<MMCRIMR_SPEC>

0x0c - Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)

§mmctimr: Reg<MMCTIMR_SPEC>

0x10 - Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)

§mmctgfsccr: Reg<MMCTGFSCCR_SPEC>

0x4c - Ethernet MMC transmitted good frames after a single collision counter

§mmctgfmsccr: Reg<MMCTGFMSCCR_SPEC>

0x50 - Ethernet MMC transmitted good frames after more than a single collision

§mmctgfcr: Reg<MMCTGFCR_SPEC>

0x68 - Ethernet MMC transmitted good frames counter register

§mmcrfcecr: Reg<MMCRFCECR_SPEC>

0x94 - Ethernet MMC received frames with CRC error counter register

§mmcrfaecr: Reg<MMCRFAECR_SPEC>

0x98 - Ethernet MMC received frames with alignment error counter register

§mmcrgufcr: Reg<MMCRGUFCR_SPEC>

0xc4 - MMC received good unicast frames counter register

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