Struct stm32f1xx_hal::timer::counter::CounterHz
source · pub struct CounterHz<TIM>(_);
Expand description
Hardware timers
Implementations§
source§impl<TIM: Instance> CounterHz<TIM>
impl<TIM: Instance> CounterHz<TIM>
pub fn start(&mut self, timeout: Hertz) -> Result<(), Error>
pub fn wait(&mut self) -> Result<(), Error>
pub fn cancel(&mut self) -> Result<(), Error>
sourcepub fn start_raw(&mut self, psc: u16, arr: u16)
pub fn start_raw(&mut self, psc: u16, arr: u16)
Restarts the timer in count down mode with user-defined prescaler and auto-reload register
sourcepub fn psc(&self) -> u16
pub fn psc(&self) -> u16
Retrieves the content of the prescaler register. The real prescaler is this value + 1.
sourcepub fn now(&self) -> MicrosDurationU32
pub fn now(&self) -> MicrosDurationU32
Returns the number of microseconds since the last update event. NOTE: This method is not a very good candidate to keep track of time, because it is very easy to lose an update event.
Methods from Deref<Target = Timer<T>>§
pub fn configure(&mut self, clocks: &Clocks)
pub fn configure_external(&mut self, clocks: &Clocks)
pub fn configure(&mut self, clocks: &Clocks)
sourcepub fn listen(&mut self, event: Event)
pub fn listen(&mut self, event: Event)
Starts listening for an event
Note, you will also have to enable the TIM2 interrupt in the NVIC to start receiving events.
sourcepub fn clear_interrupt(&mut self, event: Event)
pub fn clear_interrupt(&mut self, event: Event)
Clears interrupt associated with event
.
If the interrupt is not cleared, it will immediately retrigger after the ISR has finished.
pub fn get_interrupt(&mut self) -> Event
sourcepub fn stop_in_debug(&mut self, dbg: &mut DBG, state: bool)
pub fn stop_in_debug(&mut self, dbg: &mut DBG, state: bool)
Stopping timer in debug mode can cause troubles when sampling the signal