pub struct W(_);
Expand description
Register RTSR
writer
Implementations§
source§impl W
impl W
sourcepub fn tr0(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 0>
pub fn tr0(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 0>
Bit 0 - Rising trigger event configuration of line 0
sourcepub fn tr1(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 1>
pub fn tr1(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 1>
Bit 1 - Rising trigger event configuration of line 1
sourcepub fn tr2(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 2>
pub fn tr2(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 2>
Bit 2 - Rising trigger event configuration of line 2
sourcepub fn tr3(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 3>
pub fn tr3(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 3>
Bit 3 - Rising trigger event configuration of line 3
sourcepub fn tr4(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 4>
pub fn tr4(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 4>
Bit 4 - Rising trigger event configuration of line 4
sourcepub fn tr5(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 5>
pub fn tr5(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 5>
Bit 5 - Rising trigger event configuration of line 5
sourcepub fn tr6(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 6>
pub fn tr6(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 6>
Bit 6 - Rising trigger event configuration of line 6
sourcepub fn tr7(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 7>
pub fn tr7(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 7>
Bit 7 - Rising trigger event configuration of line 7
sourcepub fn tr8(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 8>
pub fn tr8(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 8>
Bit 8 - Rising trigger event configuration of line 8
sourcepub fn tr9(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 9>
pub fn tr9(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 9>
Bit 9 - Rising trigger event configuration of line 9
sourcepub fn tr10(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 10>
pub fn tr10(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 10>
Bit 10 - Rising trigger event configuration of line 10
sourcepub fn tr11(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 11>
pub fn tr11(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 11>
Bit 11 - Rising trigger event configuration of line 11
sourcepub fn tr12(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 12>
pub fn tr12(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 12>
Bit 12 - Rising trigger event configuration of line 12
sourcepub fn tr13(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 13>
pub fn tr13(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 13>
Bit 13 - Rising trigger event configuration of line 13
sourcepub fn tr14(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 14>
pub fn tr14(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 14>
Bit 14 - Rising trigger event configuration of line 14
sourcepub fn tr15(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 15>
pub fn tr15(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 15>
Bit 15 - Rising trigger event configuration of line 15
sourcepub fn tr16(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 16>
pub fn tr16(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 16>
Bit 16 - Rising trigger event configuration of line 16
sourcepub fn tr17(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 17>
pub fn tr17(&mut self) -> BitWriterRaw<'_, u32, RTSR_SPEC, TR0_A, BitM, 17>
Bit 17 - Rising trigger event configuration of line 17
Methods from Deref<Target = W<RTSR_SPEC>>§
sourcepub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.