Struct stm32f1xx_hal::pac::dac::RegisterBlock

source · 
pub struct RegisterBlock {
Show 13 fields
    pub cr: Reg<CR_SPEC>,
    pub swtrigr: Reg<SWTRIGR_SPEC>,
    pub dhr12r1: Reg<DHR12R1_SPEC>,
    pub dhr12l1: Reg<DHR12L1_SPEC>,
    pub dhr8r1: Reg<DHR8R1_SPEC>,
    pub dhr12r2: Reg<DHR12R2_SPEC>,
    pub dhr12l2: Reg<DHR12L2_SPEC>,
    pub dhr8r2: Reg<DHR8R2_SPEC>,
    pub dhr12rd: Reg<DHR12RD_SPEC>,
    pub dhr12ld: Reg<DHR12LD_SPEC>,
    pub dhr8rd: Reg<DHR8RD_SPEC>,
    pub dor1: Reg<DOR1_SPEC>,
    pub dor2: Reg<DOR2_SPEC>,

}
Expand description

Register block

Fields§

§cr: Reg<CR_SPEC>

0x00 - Control register (DAC_CR)

§swtrigr: Reg<SWTRIGR_SPEC>

0x04 - DAC software trigger register (DAC_SWTRIGR)

§dhr12r1: Reg<DHR12R1_SPEC>

0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

§dhr12l1: Reg<DHR12L1_SPEC>

0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

§dhr8r1: Reg<DHR8R1_SPEC>

0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

§dhr12r2: Reg<DHR12R2_SPEC>

0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

§dhr12l2: Reg<DHR12L2_SPEC>

0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

§dhr8r2: Reg<DHR8R2_SPEC>

0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

§dhr12rd: Reg<DHR12RD_SPEC>

0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

§dhr12ld: Reg<DHR12LD_SPEC>

0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

§dhr8rd: Reg<DHR8RD_SPEC>

0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

§dor1: Reg<DOR1_SPEC>

0x2c - DAC channel1 data output register (DAC_DOR1)

§dor2: Reg<DOR2_SPEC>

0x30 - DAC channel2 data output register (DAC_DOR2)

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