Module stm32f103xx::dac

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Expand description

Digital to analog converter

Modules

Control register (DAC_CR)
DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
DAC channel1 data output register (DAC_DOR1)
DAC channel2 data output register (DAC_DOR2)
DAC software trigger register (DAC_SWTRIGR)

Structs

Control register (DAC_CR)
DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
DAC channel1 data output register (DAC_DOR1)
DAC channel2 data output register (DAC_DOR2)
Register block
DAC software trigger register (DAC_SWTRIGR)