Expand description
Digital to analog converter
Modules
Control register (DAC_CR)
DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
DAC channel1 data output register (DAC_DOR1)
DAC channel2 data output register (DAC_DOR2)
DAC software trigger register (DAC_SWTRIGR)
Structs
Register block
Type Definitions
CR register accessor: an alias for Reg<CR_SPEC>
DHR8R1 register accessor: an alias for Reg<DHR8R1_SPEC>
DHR8R2 register accessor: an alias for Reg<DHR8R2_SPEC>
DHR8RD register accessor: an alias for Reg<DHR8RD_SPEC>
DHR12L1 register accessor: an alias for Reg<DHR12L1_SPEC>
DHR12L2 register accessor: an alias for Reg<DHR12L2_SPEC>
DHR12LD register accessor: an alias for Reg<DHR12LD_SPEC>
DHR12R1 register accessor: an alias for Reg<DHR12R1_SPEC>
DHR12R2 register accessor: an alias for Reg<DHR12R2_SPEC>
DHR12RD register accessor: an alias for Reg<DHR12RD_SPEC>
DOR1 register accessor: an alias for Reg<DOR1_SPEC>
DOR2 register accessor: an alias for Reg<DOR2_SPEC>
SWTRIGR register accessor: an alias for Reg<SWTRIGR_SPEC>