Enum stm32_hal2::dma::DmaInput

#[repr(usize)]
pub enum DmaInput {
    Adc1 = 9,
    Adc2 = 10,
    Tim1Ch1 = 11,
    Tim1Ch2 = 12,
    Tim1Ch3 = 13,
    Tim1Ch4 = 14,
    Tim1Up = 15,
    Tim1Trig = 16,
    Tim1Com = 17,
    Tim2Ch1 = 18,
    Tim2Ch2 = 19,
    Tim2Ch3 = 20,
    Tim2Ch4 = 21,
    Tim2Up = 22,
    Tim3Ch1 = 23,
    Tim3Ch2 = 24,
    Tim3Ch3 = 25,
    Tim3Ch4 = 26,
    Tim3Up = 27,
    Tim3Trig = 28,
    Tim4Ch1 = 29,
    Tim4Ch2 = 30,
    Tim4Ch3 = 31,
    Tim4Up = 32,
    I2c1Rx = 33,
    I2c1Tx = 34,
    I2c2Rx = 35,
    I2c2Tx = 36,
    Spi1Rx = 37,
    Spi1Tx = 38,
    Spi2Rx = 39,
    Spi2Tx = 40,
    Usart1Rx = 41,
    Usart1Tx = 42,
    Usart2Rx = 43,
    Usart2Tx = 44,
    Usart3Rx = 45,
    Usart3Tx = 46,
    Tim5Ch1 = 55,
    Tim5Ch2 = 56,
    Tim5Ch3 = 57,
    Tim5Ch4 = 58,
    Tim5Up = 59,
    Tim5Trig = 60,
    Spi3Rx = 61,
    Spi3Tx = 62,
    Uart4Rx = 63,
    Uart4Tx = 64,
    Uart5Rx = 65,
    Uart5Tx = 66,
    DacCh1 = 67,
    DacCh2 = 68,
    Tim6Up = 69,
    Tim7Up = 70,
    Uart6Rx = 71,
    Uart6Tx = 72,
    I2c3Rx = 73,
    I2c3Tx = 74,
    Dcmi = 75,
    CrypIn = 76,
    CrypOut = 77,
    HashIn = 78,
    Uart7Rx = 79,
    Uart7Tx = 80,
    Uart8Rx = 81,
    Uart8Tx = 82,
    Sai1A = 87,
    Sai1B = 88,
    Sai2A = 89,
    Sai2B = 90,
    Dfsdm1F0 = 101,
    Dfsdm1F1 = 102,
    Dfsdm1F2 = 103,
    Dfsdm1F3 = 104,
    Sai3A = 113,
    Sai3B = 114,
    Adc3 = 115,
    Uart9Rx = 116,
    Uart9Tx = 117,
    Uart10Rx = 118,
    Uart10Tx = 119,
}

A list of DMA input sources. The integer values represent their DMAMUX register value, on MCUs that use this. H743 RM, Table 121: DMAMUX1: Assignment of multiplexer inputs to resources. (Table 118 in RM0468) Note that this is only for DMAMUX1

Variants

Adc1 = 9

Adc2 = 10

Tim1Ch1 = 11

Tim1Ch2 = 12

Tim1Ch3 = 13

Tim1Ch4 = 14

Tim1Up = 15

Tim1Trig = 16

Tim1Com = 17

Tim2Ch1 = 18

Tim2Ch2 = 19

Tim2Ch3 = 20

Tim2Ch4 = 21

Tim2Up = 22

Tim3Ch1 = 23

Tim3Ch2 = 24

Tim3Ch3 = 25

Tim3Ch4 = 26

Tim3Up = 27

Tim3Trig = 28

Tim4Ch1 = 29

Tim4Ch2 = 30

Tim4Ch3 = 31

Tim4Up = 32

I2c1Rx = 33

I2c1Tx = 34

I2c2Rx = 35

I2c2Tx = 36

Spi1Rx = 37

Spi1Tx = 38

Spi2Rx = 39

Spi2Tx = 40

Usart1Rx = 41

Usart1Tx = 42

Usart2Rx = 43

Usart2Tx = 44

Usart3Rx = 45

Usart3Tx = 46

Tim5Ch1 = 55

Tim5Ch2 = 56

Tim5Ch3 = 57

Tim5Ch4 = 58

Tim5Up = 59

Tim5Trig = 60

Spi3Rx = 61

Spi3Tx = 62

Uart4Rx = 63

Uart4Tx = 64

Uart5Rx = 65

Uart5Tx = 66

DacCh1 = 67

DacCh2 = 68

Tim6Up = 69

Tim7Up = 70

Uart6Rx = 71

Uart6Tx = 72

I2c3Rx = 73

I2c3Tx = 74

Dcmi = 75

CrypIn = 76

CrypOut = 77

HashIn = 78

Uart7Rx = 79

Uart7Tx = 80

Uart8Rx = 81

Uart8Tx = 82

Sai1A = 87

Sai1B = 88

Sai2A = 89

Sai2B = 90

Dfsdm1F0 = 101

Dfsdm1F1 = 102

Dfsdm1F2 = 103

Dfsdm1F3 = 104

Sai3A = 113

Sai3B = 114

Adc3 = 115

Uart9Rx = 116

Uart9Tx = 117

Uart10Rx = 118

Uart10Tx = 119

Trait Implementations

impl Clone for DmaInput

fn clone(&self) -> DmaInput

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for DmaInput