Struct s32k144::Peripherals

pub struct Peripherals<'a> {
    pub CPUID: &'a CPUID,
    pub DCB: &'a DCB,
    pub DWT: &'a DWT,
    pub FPB: &'a FPB,
    pub FPU: &'a FPU,
    pub ITM: &'a ITM,
    pub MPU: &'a MPU,
    pub NVIC: &'a NVIC,
    pub SCB: &'a SCB,
    pub SYST: &'a SYST,
    pub TPIU: &'a TPIU,
    pub CSE_PRAM: &'a CSE_PRAM,
    pub AIPS: &'a AIPS,
    pub MSCM: &'a MSCM,
    pub DMA: &'a DMA,
    pub ERM: &'a ERM,
    pub EIM: &'a EIM,
    pub FTFC: &'a FTFC,
    pub DMAMUX: &'a DMAMUX,
    pub CAN0: &'a CAN0,
    pub CAN1: &'a CAN1,
    pub CAN2: &'a CAN2,
    pub FTM0: &'a FTM0,
    pub FTM1: &'a FTM1,
    pub FTM2: &'a FTM2,
    pub FTM3: &'a FTM3,
    pub ADC0: &'a ADC0,
    pub ADC1: &'a ADC1,
    pub LPSPI0: &'a LPSPI0,
    pub LPSPI1: &'a LPSPI1,
    pub LPSPI2: &'a LPSPI2,
    pub PDB0: &'a PDB0,
    pub PDB1: &'a PDB1,
    pub CRC: &'a CRC,
    pub LPIT0: &'a LPIT0,
    pub RTC: &'a RTC,
    pub LPTMR0: &'a LPTMR0,
    pub SIM: &'a SIM,
    pub PORTA: &'a PORTA,
    pub PORTB: &'a PORTB,
    pub PORTC: &'a PORTC,
    pub PORTD: &'a PORTD,
    pub PORTE: &'a PORTE,
    pub WDOG: &'a WDOG,
    pub FLEXIO: &'a FLEXIO,
    pub EWM: &'a EWM,
    pub TRGMUX: &'a TRGMUX,
    pub SCG: &'a SCG,
    pub PCC: &'a PCC,
    pub LPI2C0: &'a LPI2C0,
    pub LPUART0: &'a LPUART0,
    pub LPUART1: &'a LPUART1,
    pub LPUART2: &'a LPUART2,
    pub CMP0: &'a CMP0,
    pub PMC: &'a PMC,
    pub SMC: &'a SMC,
    pub RCM: &'a RCM,
    pub PTA: &'a PTA,
    pub PTB: &'a PTB,
    pub PTC: &'a PTC,
    pub PTD: &'a PTD,
    pub PTE: &'a PTE,
    pub MCM: &'a MCM,
    pub LMEM: &'a LMEM,
}

All the peripherals

Fields

CPUID: &'a CPUID

CPUID

DCB: &'a DCB

DCB

DWT: &'a DWT

DWT

FPB: &'a FPB

FPB

FPU: &'a FPU

FPU

ITM: &'a ITM

ITM

MPU: &'a MPU

MPU

NVIC: &'a NVIC

NVIC

SCB: &'a SCB

SCB

SYST: &'a SYST

SYST

TPIU: &'a TPIU

TPIU

CSE_PRAM: &'a CSE_PRAM

CSE_PRAM

AIPS: &'a AIPS

AIPS

MSCM: &'a MSCM

MSCM

DMA: &'a DMA

DMA

ERM: &'a ERM

ERM

EIM: &'a EIM

EIM

FTFC: &'a FTFC

FTFC

DMAMUX: &'a DMAMUX

DMAMUX

CAN0: &'a CAN0

CAN0

CAN1: &'a CAN1

CAN1

CAN2: &'a CAN2

CAN2

FTM0: &'a FTM0

FTM0

FTM1: &'a FTM1

FTM1

FTM2: &'a FTM2

FTM2

FTM3: &'a FTM3

FTM3

ADC0: &'a ADC0

ADC0

ADC1: &'a ADC1

ADC1

LPSPI0: &'a LPSPI0

LPSPI0

LPSPI1: &'a LPSPI1

LPSPI1

LPSPI2: &'a LPSPI2

LPSPI2

PDB0: &'a PDB0

PDB0

PDB1: &'a PDB1

PDB1

CRC: &'a CRC

CRC

LPIT0: &'a LPIT0

LPIT0

RTC: &'a RTC

RTC

LPTMR0: &'a LPTMR0

LPTMR0

SIM: &'a SIM

SIM

PORTA: &'a PORTA

PORTA

PORTB: &'a PORTB

PORTB

PORTC: &'a PORTC

PORTC

PORTD: &'a PORTD

PORTD

PORTE: &'a PORTE

PORTE

WDOG: &'a WDOG

WDOG

FLEXIO: &'a FLEXIO

FLEXIO

EWM: &'a EWM

EWM

TRGMUX: &'a TRGMUX

TRGMUX

SCG: &'a SCG

SCG

PCC: &'a PCC

PCC

LPI2C0: &'a LPI2C0

LPI2C0

LPUART0: &'a LPUART0

LPUART0

LPUART1: &'a LPUART1

LPUART1

LPUART2: &'a LPUART2

LPUART2

CMP0: &'a CMP0

CMP0

PMC: &'a PMC

PMC

SMC: &'a SMC

SMC

RCM: &'a RCM

RCM

PTA: &'a PTA

PTA

PTB: &'a PTB

PTB

PTC: &'a PTC

PTC

PTD: &'a PTD

PTD

PTE: &'a PTE

PTE

MCM: &'a MCM

MCM

LMEM: &'a LMEM

LMEM

Methods

impl<'a> Peripherals<'a>

unsafe fn all() -> Self

Grants access to all the peripherals