Enum rustacuda::device::DeviceAttribute [−][src]
#[repr(u32)]
pub enum DeviceAttribute {
Show 103 variants
MaxThreadsPerBlock,
MaxBlockDimX,
MaxBlockDimY,
MaxBlockDimZ,
MaxGridDimX,
MaxGridDimY,
MaxGridDimZ,
MaxSharedMemoryPerBlock,
TotalConstantMemory,
WarpSize,
MaxPitch,
MaxRegistersPerBlock,
ClockRate,
TextureAlignment,
MultiprocessorCount,
KernelExecTimeout,
Integrated,
CanMapHostMemory,
ComputeMode,
MaximumTexture1DWidth,
MaximumTexture2DWidth,
MaximumTexture2DHeight,
MaximumTexture3DWidth,
MaximumTexture3DHeight,
MaximumTexture3DDepth,
MaximumTexture2DLayeredWidth,
MaximumTexture2DLayeredHeight,
MaximumTexture2DLayeredLayers,
SurfaceAlignment,
ConcurrentKernels,
EccEnabled,
PciBusId,
PciDeviceId,
TccDriver,
MemoryClockRate,
GlobalMemoryBusWidth,
L2CacheSize,
MaxThreadsPerMultiprocessor,
AsyncEngineCount,
UnifiedAddressing,
MaximumTexture1DLayeredWidth,
MaximumTexture1DLayeredLayers,
MaximumTexture2DGatherWidth,
MaximumTexture2DGatherHeight,
MaximumTexture3DWidthAlternate,
MaximumTexture3DHeightAlternate,
MaximumTexture3DDepthAlternate,
PciDomainId,
TexturePitchAlignment,
MaximumTextureCubemapWidth,
MaximumTextureCubemapLayeredWidth,
MaximumTextureCubemapLayeredLayers,
MaximumSurface1DWidth,
MaximumSurface2DWidth,
MaximumSurface2DHeight,
MaximumSurface3DWidth,
MaximumSurface3DHeight,
MaximumSurface3DDepth,
MaximumSurface1DLayeredWidth,
MaximumSurface1DLayeredLayers,
MaximumSurface2DLayeredWidth,
MaximumSurface2DLayeredHeight,
MaximumSurface2DLayeredLayers,
MaximumSurfacecubemapWidth,
MaximumSurfacecubemapLayeredWidth,
MaximumSurfacecubemapLayeredLayers,
MaximumTexture1DLinearWidth,
MaximumTexture2DLinearWidth,
MaximumTexture2DLinearHeight,
MaximumTexture2DLinearPitch,
MaximumTexture2DMipmappedWidth,
MaximumTexture2DMipmappedHeight,
ComputeCapabilityMajor,
ComputeCapabilityMinor,
MaximumTexture1DMipmappedWidth,
StreamPrioritiesSupported,
GlobalL1CacheSupported,
LocalL1CacheSupported,
MaxSharedMemoryPerMultiprocessor,
MaxRegistersPerMultiprocessor,
ManagedMemory,
MultiGpuBoard,
MultiGpuBoardGroupId,
HostNativeAtomicSupported,
SingleToDoublePrecisionPerfRatio,
PageableMemoryAccess,
ConcurrentManagedAccess,
ComputePreemptionSupported,
CanUseHostPointerForRegisteredMem,
CanUseStreamMemOps,
CanUse64BitStreamMemOps,
CanUseStreamWaitValueNor,
CooperativeLaunch,
CooperativeMultiDeviceLaunch,
MaxSharedMemoryPerBlockOptin,
CanFlushRemoteWrites,
HostRegisterSupported,
PageableMemoryAccessUsesHostPageTable,
DirectManagedMemAccessFromhost,
VirtualMemoryManagementSupported,
HandleTypePosixFileDescriptorSupported,
HandleTypeWin32HandleSupported,
HandleTypeWin32KmtHandleSupported,
// some variants omitted
}Expand description
All supported device attributes for Device::get_attribute
Variants
Maximum number of threads per block
Maximum x-dimension of a block
Maximum y-dimension of a block
Maximum z-dimension of a block
Maximum x-dimension of a grid
Maximum y-dimension of a grid
Maximum z-dimension of a grid
Maximum amount of shared memory available to a thread block in bytes
Memory available on device for constant variables in a kernel in bytes
Warp size in threads
Maximum pitch in bytes allowed by the memory copy functions that involve memory regions allocated through cuMemAllocPitch()
Maximum number of 32-bit registers available to a thread block
Typical clock frequency in kilohertz
Alignment requirement for textures
Number of multiprocessors on device.
Specifies whether there is a run time limit on kernels
Device is integrated with host memory
Device can map host memory into CUDA address space
Compute Mode
Maximum 1D texture width
Maximum 2D texture width
Maximum 2D texture height
Maximum 3D texture width
Maximum 3D texture height
Maximum 3D texture depth
Maximum 2D layered texture width
Maximum 2D layered texture height
Maximum layers in a 2D layered texture
Alignment requirement for surfaces
Device can possibly execute multiple kernels concurrently
Device has ECC support enabled
PCI bus ID of the device
PCI device ID of the device
Device is using TCC driver model
Peak memory clock frequency in kilohertz
Global memory bus width in bits
Size of L2 cache in bytes.
Maximum resident threads per multiprocessor
Number of asynchronous engines
Device shares a unified address space with the host
Maximum 1D layered texture width
Maximum layers in a 1D layered texture
Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set
Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set
Alternate maximum 3D texture width
Alternate maximum 3D texture height
Alternate maximum 3D texture depth
PCI domain ID of the device
Pitch alignment requirement for textures
Maximum cubemap texture width/height
Maximum cubemap layered texture width/height
Maximum layers in a cubemap layered texture
Maximum 1D surface width
Maximum 2D surface width
Maximum 2D surface height
Maximum 3D surface width
Maximum 3D surface height
Maximum 3D surface depth
Maximum 1D layered surface width
Maximum layers in a 1D layered surface
Maximum 2D layered surface width
Maximum 2D layered surface height
Maximum layers in a 2D layered surface
Maximum cubemap surface width
Maximum cubemap layered surface width
Maximum layers in a cubemap layered surface
Maximum 1D linear texture width
Maximum 2D linear texture width
Maximum 2D linear texture height
Maximum 2D linear texture pitch in bytes
Maximum mipmapped 2D texture height
Maximum mipmapped 2D texture width
Major compute capability version number
Minor compute capability version number
Maximum mipammed 1D texture width
Device supports stream priorities
Device supports caching globals in L1
Device supports caching locals in L1
Maximum shared memory available per multiprocessor in bytes
Maximum number of 32-bit registers available per multiprocessor
Device can allocate managed memory on this system
Device is on a multi-GPU board
Unique ID for a group of devices on the same multi-GPU board
Link between the device and the host supports native atomic operations (this is a placeholder attribute and is not supported on any current hardware)
Ratio of single precision performance (in floating-point operations per second) to double precision performance
Device supports coherently accessing pageable memory without calling cudaHostRegister on it.
Device can coherently access managed memory concurrently with the CPU
Device supports compute preemption
Device can access host registered memory at the same virtual address as the CPU
Stream memory operations are supported.
64-bit stream memory operations are supported.
Wait value NOR is supported
Supports launching cooperative kernels
Supports launching cooperative kernels on multiple devices.
Maximum opt-in shared memory per block.
Stream memory operations can wait for flush.
Device supports host memory registration
Device accesses pageable memory via the host page tables
Device supports direct access to device memory without migration
Device supports virual memory management APIs
Device supports exporting memory to a posix file descriptor
Device supports exporting memory to a Win32 NT handle
Device supports exporting memory to a Win32 KMT handle
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for DeviceAttribute
impl Send for DeviceAttribute
impl Sync for DeviceAttribute
impl Unpin for DeviceAttribute
impl UnwindSafe for DeviceAttribute
Blanket Implementations
Mutably borrows from an owned value. Read more