Enum rustacuda::device::DeviceAttribute

#[repr(u32)]
pub enum DeviceAttribute {
    MaxThreadsPerBlock,
    MaxBlockDimX,
    MaxBlockDimY,
    MaxBlockDimZ,
    MaxGridDimX,
    MaxGridDimY,
    MaxGridDimZ,
    MaxSharedMemoryPerBlock,
    TotalConstantMemory,
    WarpSize,
    MaxPitch,
    MaxRegistersPerBlock,
    ClockRate,
    TextureAlignment,
    MultiprocessorCount,
    KernelExecTimeout,
    Integrated,
    CanMapHostMemory,
    ComputeMode,
    MaximumTexture1DWidth,
    MaximumTexture2DWidth,
    MaximumTexture2DHeight,
    MaximumTexture3DWidth,
    MaximumTexture3DHeight,
    MaximumTexture3DDepth,
    MaximumTexture2DLayeredWidth,
    MaximumTexture2DLayeredHeight,
    MaximumTexture2DLayeredLayers,
    SurfaceAlignment,
    ConcurrentKernels,
    EccEnabled,
    PciBusId,
    PciDeviceId,
    TccDriver,
    MemoryClockRate,
    GlobalMemoryBusWidth,
    L2CacheSize,
    MaxThreadsPerMultiprocessor,
    AsyncEngineCount,
    UnifiedAddressing,
    MaximumTexture1DLayeredWidth,
    MaximumTexture1DLayeredLayers,
    MaximumTexture2DGatherWidth,
    MaximumTexture2DGatherHeight,
    MaximumTexture3DWidthAlternate,
    MaximumTexture3DHeightAlternate,
    MaximumTexture3DDepthAlternate,
    PciDomainId,
    TexturePitchAlignment,
    MaximumTexturecubemapWidth,
    MaximumTexturecubemapLayeredWidth,
    MaximumTexturecubemapLayeredLayers,
    MaximumSurface1DWidth,
    MaximumSurface2DWidth,
    MaximumSurface2DHeight,
    MaximumSurface3DWidth,
    MaximumSurface3DHeight,
    MaximumSurface3DDepth,
    MaximumSurface1DLayeredWidth,
    MaximumSurface1DLayeredLayers,
    MaximumSurface2DLayeredWidth,
    MaximumSurface2DLayeredHeight,
    MaximumSurface2DLayeredLayers,
    MaximumSurfacecubemapWidth,
    MaximumSurfacecubemapLayeredWidth,
    MaximumSurfacecubemapLayeredLayers,
    MaximumTexture1DLinearWidth,
    MaximumTexture2DLinearWidth,
    MaximumTexture2DLinearHeight,
    MaximumTexture2DLinearPitch,
    MaximumTexture2DMipmappedWidth,
    MaximumTexture2DMipmappedHeight,
    ComputeCapabilityMajor,
    ComputeCapabilityMinor,
    MaximumTexture1DMipmappedWidth,
    StreamPrioritiesSupported,
    GlobalL1CacheSupported,
    LocalL1CacheSupported,
    MaxSharedMemoryPerMultiprocessor,
    MaxRegistersPerMultiprocessor,
    ManagedMemory,
    MultiGpuBoard,
    MultiGpuBoardGroupId,
    HostNativeAtomicSupported,
    SingleToDoublePrecisionPerfRatio,
    PageableMemoryAccess,
    ConcurrentManagedAccess,
    ComputePreemptionSupported,
    CanUseHostPointerForRegisteredMem,
    // some variants omitted
}

All supported device attributes for Device::get_attribute

Variants

MaxThreadsPerBlock

Maximum number of threads per block

MaxBlockDimX

Maximum x-dimension of a block

MaxBlockDimY

Maximum y-dimension of a block

MaxBlockDimZ

Maximum z-dimension of a block

MaxGridDimX

Maximum x-dimension of a grid

MaxGridDimY

Maximum y-dimension of a grid

MaxGridDimZ

Maximum a-dimension of a grid

MaxSharedMemoryPerBlock

Maximum amount of shared memory available to a thread block in bytes

TotalConstantMemory

Memory available on device for constant variables in a kernel in bytes

WarpSize

Warp size in threads

MaxPitch

Maximum pitch in bytes allowed by the memory copy functions that involve memory regions allocated through cuMemAllocPitch()

MaxRegistersPerBlock

Maximum number of 32-bit registers available to a thread block

ClockRate

Typical clock frequency in kilohertz

TextureAlignment

Alignment requirement for textures

MultiprocessorCount

Number of multiprocessors on device.

KernelExecTimeout

Specifies whether there is a run time limit on kernels

Integrated

Device is integrated with host memory

CanMapHostMemory

Device can map host memory into CUDA address space

ComputeMode

Compute Mode

MaximumTexture1DWidth

Maximum 1D texture width

MaximumTexture2DWidth

Maximum 2D texture width

MaximumTexture2DHeight

Maximum 2D texture height

MaximumTexture3DWidth

Maximum 3D texture width

MaximumTexture3DHeight

Maximum 3D texture height

MaximumTexture3DDepth

Maximum 3D texture depth

MaximumTexture2DLayeredWidth

Maximum 2D layered texture width

MaximumTexture2DLayeredHeight

Maximum 2D layered texture height

MaximumTexture2DLayeredLayers

Maximum layers in a 2D layered texture

SurfaceAlignment

Alignment requirement for surfaces

ConcurrentKernels

Device can possibly execute multiple kernels concurrently

EccEnabled

Device has ECC support enabled

PciBusId

PCI bus ID of the device

PciDeviceId

PCI device ID of the device

TccDriver

Device is using TCC driver model

MemoryClockRate

Peak memory clock frequency in kilohertz

GlobalMemoryBusWidth

Global memory bus width in bits

L2CacheSize

Size of L2 cache in bytes.

MaxThreadsPerMultiprocessor

Maximum resident threads per multiprocessor

AsyncEngineCount

Number of asynchronous engines

UnifiedAddressing

Device shares a unified address space with the host

MaximumTexture1DLayeredWidth

Maximum 1D layered texture width

MaximumTexture1DLayeredLayers

Maximum layers in a 1D layered texture

MaximumTexture2DGatherWidth

Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set

MaximumTexture2DGatherHeight

Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set

MaximumTexture3DWidthAlternate

Alternate maximum 3D texture width

MaximumTexture3DHeightAlternate

Alternate maximum 3D texture height

MaximumTexture3DDepthAlternate

Alternate maximum 3D texture depth

PciDomainId

PCI domain ID of the device

TexturePitchAlignment

Pitch alignment requirement for textures

MaximumTexturecubemapWidth

Maximum cubemap texture width/height

MaximumTexturecubemapLayeredWidth

Maximum cubemap layered texture width/height

MaximumTexturecubemapLayeredLayers

Maximum layers in a cubemap layered texture

MaximumSurface1DWidth

Maximum 1D surface width

MaximumSurface2DWidth

Maximum 2D surface width

MaximumSurface2DHeight

Maximum 2D surface height

MaximumSurface3DWidth

Maximum 3D surface width

MaximumSurface3DHeight

Maximum 3D surface height

MaximumSurface3DDepth

Maximum 3D surface depth

MaximumSurface1DLayeredWidth

Maximum 1D layered surface width

MaximumSurface1DLayeredLayers

Maximum layers in a 1D layered surface

MaximumSurface2DLayeredWidth

Maximum 2D layered surface width

MaximumSurface2DLayeredHeight

Maximum 2D layered surface height

MaximumSurface2DLayeredLayers

Maximum layers in a 2D layered surface

MaximumSurfacecubemapWidth

Maximum cubemap surface width

MaximumSurfacecubemapLayeredWidth

Maximum cubemap layered surface width

MaximumSurfacecubemapLayeredLayers

Maximum layers in a cubemap layered surface

MaximumTexture1DLinearWidth

Maximum 1D linear texture width

MaximumTexture2DLinearWidth

Maximum 2D linear texture width

MaximumTexture2DLinearHeight

Maximum 2D linear texture height

MaximumTexture2DLinearPitch

Maximum 2D linear texture pitch in bytes

MaximumTexture2DMipmappedWidth

Maximum mipmapped 2D texture height

MaximumTexture2DMipmappedHeight

Maximum mipmapped 2D texture width

ComputeCapabilityMajor

Major compute capability version number

ComputeCapabilityMinor

Minor compute capability version number

MaximumTexture1DMipmappedWidth

Maximum mipammed 1D texture width

StreamPrioritiesSupported

Device supports stream priorities

GlobalL1CacheSupported

Device supports caching globals in L1

LocalL1CacheSupported

Device supports caching locals in L1

MaxSharedMemoryPerMultiprocessor

Maximum shared memory available per multiprocessor in bytes

MaxRegistersPerMultiprocessor

Maximum number of 32-bit registers available per multiprocessor

ManagedMemory

Device can allocate managed memory on this system

MultiGpuBoard

Device is on a multi-GPU board

MultiGpuBoardGroupId

Unique ID for a group of devices on the same multi-GPU board

HostNativeAtomicSupported

Link between the device and the host supports native atomic operations (this is a placeholder attribute and is not supported on any current hardware)

SingleToDoublePrecisionPerfRatio

Ratio of single precision performance (in floating-point operations per second) to double precision performance

PageableMemoryAccess

Device supports coherently accessing pageable memory without calling cudaHostRegister on it.

ConcurrentManagedAccess

Device can coherently access managed memory concurrently with the CPU

ComputePreemptionSupported

Device supports compute preemption

CanUseHostPointerForRegisteredMem

Device can access host registered memory at the same virtual address as the CPU

Trait Implementations

impl Clone for DeviceAttribute

fn clone(&self) -> DeviceAttribute

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DeviceAttribute

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for DeviceAttribute

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)where
    H: Hasher,
    Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq<DeviceAttribute> for DeviceAttribute

fn eq(&self, other: &DeviceAttribute) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for DeviceAttribute

impl Eq for DeviceAttribute

impl StructuralEq for DeviceAttribute

impl StructuralPartialEq for DeviceAttribute