Build #1842126 2025-03-08 14:39:39
# rustc version
rustc 1.87.0-nightly (f5a1ef712 2025-03-07)# docs.rs version
docsrs 0.6.0 (004a02c4 2025-03-05)# build log
[INFO] running `Command { std: "docker" "create" "-v" "/home/cratesfyi/workspace-builder/builds/rust_hdl_lib_core-0.44.1/target:/opt/rustwide/target:rw,Z" "-v" "/home/cratesfyi/workspace-builder/builds/rust_hdl_lib_core-0.44.1/source:/opt/rustwide/workdir:ro,Z" "-v" "/home/cratesfyi/workspace-builder/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/home/cratesfyi/workspace-builder/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "DOCS_RS=1" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-w" "/opt/rustwide/workdir" "-m" "6442450944" "--cpus" "6" "--user" "1001:1001" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:1680c8fbd8dfb46fcd6d22e546df16ab0e007457dc29fcd9e987cdd5077fd1af" "/opt/rustwide/cargo-home/bin/cargo" "+nightly" "rustdoc" "--lib" "-Zrustdoc-map" "--config" "build.rustdocflags=[\"--cfg\", \"docsrs\", \"-Z\", \"unstable-options\", \"--emit=invocation-specific\", \"--resource-suffix\", \"-20250307-1.87.0-nightly-f5a1ef712\", \"--static-root-path\", \"/-/rustdoc.static/\", \"--cap-lints\", \"warn\", \"--extern-html-root-takes-precedence\"]" "--offline" "-Zunstable-options" "--config=doc.extern-map.registries.crates-io=\"https://docs.rs/{pkg_name}/{version}/x86_64-unknown-linux-gnu\"" "-Zrustdoc-scrape-examples" "-j6" "--target" "x86_64-unknown-linux-gnu", kill_on_drop: false }`
[INFO] [stderr] WARNING: Your kernel does not support swap limit capabilities or the cgroup is not mounted. Memory limited without swap.
[INFO] [stdout] 25201f47ba88b1fb242309e0d7412762c73209cadb1e2263faa6526bdf7698f5
[INFO] running `Command { std: "docker" "start" "-a" "25201f47ba88b1fb242309e0d7412762c73209cadb1e2263faa6526bdf7698f5", kill_on_drop: false }`
[INFO] [stderr] warning: target filter specified, but no targets matched; this is a no-op
[INFO] [stderr] Documenting rust_hdl_lib_core v0.44.1 (/opt/rustwide/workdir)
[INFO] [stderr] warning: unresolved link to `hdl`
[INFO] [stderr] --> src/ast.rs:33:28
[INFO] [stderr] |
[INFO] [stderr] 33 | /// implementation of the [hdl] function in the [Logic] trait. This
[INFO] [stderr] | ^^^ no item named `hdl` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr] = note: `#[warn(rustdoc::broken_intra_doc_links)]` on by default
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:33:50
[INFO] [stderr] |
[INFO] [stderr] 33 | /// implementation of the [hdl] function in the [Logic] trait. This
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `LogicBlock`
[INFO] [stderr] --> src/ast.rs:73:22
[INFO] [stderr] |
[INFO] [stderr] 73 | /// We will use the [LogicBlock] derive macro to add the [Logic]
[INFO] [stderr] | ^^^^^^^^^^ no item named `LogicBlock` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:73:59
[INFO] [stderr] |
[INFO] [stderr] 73 | /// We will use the [LogicBlock] derive macro to add the [Logic]
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:76:10
[INFO] [stderr] |
[INFO] [stderr] 76 | /// The [Logic] trait for this circuit will need to be implemented
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:102:10
[INFO] [stderr] |
[INFO] [stderr] 102 | /// The [Logic] trait requires 3 methods [Logic::update], [Logic::connect],
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::update`
[INFO] [stderr] --> src/ast.rs:102:43
[INFO] [stderr] |
[INFO] [stderr] 102 | /// The [Logic] trait requires 3 methods [Logic::update], [Logic::connect],
[INFO] [stderr] | ^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::connect`
[INFO] [stderr] --> src/ast.rs:102:60
[INFO] [stderr] |
[INFO] [stderr] 102 | /// The [Logic] trait requires 3 methods [Logic::update], [Logic::connect],
[INFO] [stderr] | ^^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::hdl`
[INFO] [stderr] --> src/ast.rs:103:10
[INFO] [stderr] |
[INFO] [stderr] 103 | /// and [Logic::hdl]. The [Logic::update] method is used for simulation, and
[INFO] [stderr] | ^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::update`
[INFO] [stderr] --> src/ast.rs:103:29
[INFO] [stderr] |
[INFO] [stderr] 103 | /// and [Logic::hdl]. The [Logic::update] method is used for simulation, and
[INFO] [stderr] | ^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::connect`
[INFO] [stderr] --> src/ast.rs:105:47
[INFO] [stderr] |
[INFO] [stderr] 105 | /// the default implementation of this. The [Logic::connect] method is used
[INFO] [stderr] | ^^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::connect`
[INFO] [stderr] --> src/ast.rs:111:41
[INFO] [stderr] |
[INFO] [stderr] 111 | /// connected. For our black box, the [Logic::connect] trait implementation
[INFO] [stderr] | ^^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `hdl`
[INFO] [stderr] --> src/ast.rs:331:75
[INFO] [stderr] |
[INFO] [stderr] 331 | /// To use the [Wrapper] you must provide a custom implementation of the [hdl]
[INFO] [stderr] | ^^^ no item named `hdl` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:332:22
[INFO] [stderr] |
[INFO] [stderr] 332 | /// function in the [Logic] trait. The [Wrapper] variant has two members.
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `code`
[INFO] [stderr] --> src/ast.rs:333:30
[INFO] [stderr] |
[INFO] [stderr] 333 | /// The first member is the [code] where you can write the Verilog glue
[INFO] [stderr] | ^^^^ no item named `code` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `cores`
[INFO] [stderr] --> src/ast.rs:335:74
[INFO] [stderr] |
[INFO] [stderr] 335 | /// inputs and outputs of the RustHDL object. The second member is the [cores]
[INFO] [stderr] | ^^^^^ no item named `cores` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `LogicBlock`
[INFO] [stderr] --> src/ast.rs:376:10
[INFO] [stderr] |
[INFO] [stderr] 376 | /// the [LogicBlock] derive macro to add the [Logic]
[INFO] [stderr] | ^^^^^^^^^^ no item named `LogicBlock` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:376:47
[INFO] [stderr] |
[INFO] [stderr] 376 | /// the [LogicBlock] derive macro to add the [Logic]
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:379:10
[INFO] [stderr] |
[INFO] [stderr] 379 | /// The [Logic] trait for this circuit will need to be implemented
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic`
[INFO] [stderr] --> src/ast.rs:406:10
[INFO] [stderr] |
[INFO] [stderr] 406 | /// The [Logic] trait requires 3 methods [Logic::update], [Logic::connect],
[INFO] [stderr] | ^^^^^ no item named `Logic` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::update`
[INFO] [stderr] --> src/ast.rs:406:43
[INFO] [stderr] |
[INFO] [stderr] 406 | /// The [Logic] trait requires 3 methods [Logic::update], [Logic::connect],
[INFO] [stderr] | ^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::connect`
[INFO] [stderr] --> src/ast.rs:406:60
[INFO] [stderr] |
[INFO] [stderr] 406 | /// The [Logic] trait requires 3 methods [Logic::update], [Logic::connect],
[INFO] [stderr] | ^^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::hdl`
[INFO] [stderr] --> src/ast.rs:407:10
[INFO] [stderr] |
[INFO] [stderr] 407 | /// and [Logic::hdl]. The [Logic::update] method is used for simulation, and
[INFO] [stderr] | ^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::update`
[INFO] [stderr] --> src/ast.rs:407:29
[INFO] [stderr] |
[INFO] [stderr] 407 | /// and [Logic::hdl]. The [Logic::update] method is used for simulation, and
[INFO] [stderr] | ^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Logic::connect`
[INFO] [stderr] --> src/ast.rs:409:47
[INFO] [stderr] |
[INFO] [stderr] 409 | /// the default implementation of this. The [Logic::connect] method is used
[INFO] [stderr] | ^^^^^^^^^^^^^^ no item named `Logic` in scope
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Empty`
[INFO] [stderr] --> src/ast.rs:568:14
[INFO] [stderr] |
[INFO] [stderr] 568 | /// Use [Empty] when you do not want a module represented in Verilog at all
[INFO] [stderr] | ^^^^^ no item named `Empty` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] The [Bits] type is used to capture values with arbitrarily large (but known) bit length
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] To model this behavior in RustHDL, we have the [Bits] type, which attempts to be as close
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] you should be able to think of it as a bit of arbitrary length. Note that the [Bits]
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] For the most part, the [Bits] type is meant to act like a `u32` or `u128` type as far
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] # Constructing [Bits]
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] There are several ways to construct a [Bits] type. It includes an implementation of
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `ToBits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] There is also the [ToBits] trait, which is implemented on the basic unsigned integer types.
[INFO] [stderr] ^^^^^^
[INFO] [stderr] = note: no item named `ToBits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] Only a subset of operations are defined for [Bits]. These are the operations that can
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] operate between [Bits] types and other [Bits] of the _same width_, or you can
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] operate between [Bits] types and other [Bits] of the _same width_, or you can
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] And now a second example that uses two [Bits] values
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `x`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] In this case, the addition of 1 caused [x] to wrap to all zeros. This is totally normal,
[INFO] [stderr] ^
[INFO] [stderr] = note: no item named `x` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] determined by the [Bits] width.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] However, you cannot combine two different width [Bits] values in a single expression.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Wrapping`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] gates. Subtraction operates much like the [Wrapping] class. Note that overflow and underflow
[INFO] [stderr] ^^^^^^^^
[INFO] [stderr] = note: no item named `Wrapping` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] bitwidth of the computation will be driven by the width of the [Bits] in the expression.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] You can combine [Bits] using the and operator `&`. In general, avoid using the shortcut
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] (or shortcut OR) operator `||` is not supported for [Bits], as it is only defined for
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] The caveat about mixing [Bits] of different widths still applies.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] The equality operator `==` can compare two [Bits] for bit-wise equality.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] Again, it is a compile time failure to attempt to compare [Bits] of different
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] bitwidth of the [Bits] value.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] The [Bits] type only supports unsigned comparisons. If you compare a [Bits] value
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] The [Bits] type only supports unsigned comparisons. If you compare a [Bits] value
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Signed`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] values, use [Signed].
[INFO] [stderr] ^^^^^^
[INFO] [stderr] = note: no item named `Signed` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Bits`
[INFO] [stderr] --> src/lib.rs:4:1
[INFO] [stderr] |
[INFO] [stderr] 4 | / /// Module that supports arbitrary width bit vectors
[INFO] [stderr] 5 | | pub mod bits;
[INFO] [stderr] 6 | | #[doc(hidden)]
[INFO] [stderr] 7 | | pub mod bitvec;
[INFO] [stderr] ... |
[INFO] [stderr] |
[INFO] [stderr] = note: the link appears in this line:
[INFO] [stderr]
[INFO] [stderr] of the [Bits] being compared to.
[INFO] [stderr] ^^^^
[INFO] [stderr] = note: no item named `Bits` in scope
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `to_bits`
[INFO] [stderr] --> src/bits.rs:364:35
[INFO] [stderr] |
[INFO] [stderr] 364 | /// Rust notation, and using the [to_bits] trait to convert it to a [Bits] type.
[INFO] [stderr] | ^^^^^^^ no item named `to_bits` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `N`
[INFO] [stderr] --> src/bits.rs:422:48
[INFO] [stderr] |
[INFO] [stderr] 422 | /// The [Bits] type holds a bit array of size [N].
[INFO] [stderr] | ^ no item named `N` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Signed`
[INFO] [stderr] --> src/bits.rs:721:48
[INFO] [stderr] |
[INFO] [stderr] 721 | /// want to work with signed bit vectors, use [Signed] instead.
[INFO] [stderr] | ^^^^^^ no item named `Signed` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `any`
[INFO] [stderr] --> src/bits.rs:777:14
[INFO] [stderr] |
[INFO] [stderr] 777 | /// The [any] function returns true if any of the
[INFO] [stderr] | ^^^ no item named `any` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `all`
[INFO] [stderr] --> src/bits.rs:796:14
[INFO] [stderr] |
[INFO] [stderr] 796 | /// The [all] function returns true if all of the individual
[INFO] [stderr] | ^^^ no item named `all` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `xor`
[INFO] [stderr] --> src/bits.rs:815:14
[INFO] [stderr] |
[INFO] [stderr] 815 | /// The [xor] function computes the exclusive OR of all
[INFO] [stderr] | ^^^ no item named `xor` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `index`
[INFO] [stderr] --> src/bits.rs:833:14
[INFO] [stderr] |
[INFO] [stderr] 833 | /// The [index] function is used when a [Bits] is going
[INFO] [stderr] | ^^^^^ no item named `index` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `count`
[INFO] [stderr] --> src/bits.rs:878:54
[INFO] [stderr] |
[INFO] [stderr] 878 | /// A [Bits<256>] for example, cannot represent [count]
[INFO] [stderr] | ^^^^^ no item named `count` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `index`
[INFO] [stderr] --> src/bits.rs:889:22
[INFO] [stderr] |
[INFO] [stderr] 889 | /// Extract the [index] bit from the given [Bits]. This will
[INFO] [stderr] | ^^^^^ no item named `index` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `index`
[INFO] [stderr] --> src/bits.rs:890:39
[INFO] [stderr] |
[INFO] [stderr] 890 | /// cause a runtime panic if the [index] bit is out of range
[INFO] [stderr] | ^^^^^ no item named `index` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `M`
[INFO] [stderr] --> src/bits.rs:929:52
[INFO] [stderr] |
[INFO] [stderr] 929 | /// of the result must be fixed (the argument [M]), and only the offset
[INFO] [stderr] | ^ no item named `M` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `N`
[INFO] [stderr] --> src/bits.rs:961:47
[INFO] [stderr] |
[INFO] [stderr] 961 | /// Returns a [Bits] value that contains [N] ones.
[INFO] [stderr] | ^ no item named `N` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `DFF`
[INFO] [stderr] --> src/clock.rs:6:39
[INFO] [stderr] |
[INFO] [stderr] 6 | /// ports on synchronous logic (like [DFF] or [RAM]).
[INFO] [stderr] | ^^^ no item named `DFF` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `RAM`
[INFO] [stderr] --> src/clock.rs:6:48
[INFO] [stderr] |
[INFO] [stderr] 6 | /// ports on synchronous logic (like [DFF] or [RAM]).
[INFO] [stderr] | ^^^ no item named `RAM` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Signal`
[INFO] [stderr] --> src/direction.rs:8:42
[INFO] [stderr] |
[INFO] [stderr] 8 | /// This direction marker is used for a [Signal] that is
[INFO] [stderr] | ^^^^^^ no item named `Signal` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `Signal`
[INFO] [stderr] --> src/direction.rs:24:42
[INFO] [stderr] |
[INFO] [stderr] 24 | /// This direction marker is used for a [Signal] that
[INFO] [stderr] | ^^^^^^ no item named `Signal` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `clock`
[INFO] [stderr] --> src/clock.rs:41:10
[INFO] [stderr] |
[INFO] [stderr] 41 | /// The [clock!] macro is used to connect a set of devices to a common clock.
[INFO] [stderr] | ^^^^^^ no item named `clock` in scope
[INFO] [stderr] |
[INFO] [stderr] = note: `macro_rules` named `clock` exists in this crate, but it is not in scope at this link's location
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `DFF`
[INFO] [stderr] --> src/clock.rs:81:25
[INFO] [stderr] |
[INFO] [stderr] 81 | /// When you have many [DFF]s or several complex sub-circuits, the `clock!` macro can make it
[INFO] [stderr] | ^^^ no item named `DFF` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: unresolved link to `RefUnwindSafe`
[INFO] [stderr] --> src/simulate.rs:233:10
[INFO] [stderr] |
[INFO] [stderr] 233 | /// [RefUnwindSafe] (no FFI).
[INFO] [stderr] | ^^^^^^^^^^^^^ no item named `RefUnwindSafe` in scope
[INFO] [stderr] |
[INFO] [stderr] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
[INFO] [stderr]
[INFO] [stderr] warning: `rust_hdl_lib_core` (lib doc) generated 71 warnings
[INFO] [stderr] Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.76s
[INFO] [stderr] warning: the following packages contain code that will be rejected by a future version of Rust: svg v0.10.0
[INFO] [stderr] note: to see what the problems were, use the option `--future-incompat-report`, or run `cargo report future-incompatibilities --id 1`
[INFO] [stderr] Generated /opt/rustwide/target/x86_64-unknown-linux-gnu/doc/rust_hdl_lib_core/index.html
[INFO] running `Command { std: "docker" "inspect" "25201f47ba88b1fb242309e0d7412762c73209cadb1e2263faa6526bdf7698f5", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "rm" "-f" "25201f47ba88b1fb242309e0d7412762c73209cadb1e2263faa6526bdf7698f5", kill_on_drop: false }`
[INFO] [stdout] 25201f47ba88b1fb242309e0d7412762c73209cadb1e2263faa6526bdf7698f5