Trait ruduino::modules::HardwareSpi[−][src]

pub trait HardwareSpi {
    type MasterInSlaveOut: Pin;
    type MasterOutSlaveIn: Pin;
    type Clock: Pin;
    type SlaveSelect: Pin;
    type ControlRegister: Register<T = u8>;
    type StatusRegister: Register<T = u8>;
    type DataRegister: Register<T = u8>;
    fn setup_master(clock: u32) { ... }

    fn setup_slave(clock: u32) { ... }

    fn setup_common(clock: u32) { ... }

    fn set_clock(clock: u32) { ... }

    fn enable_interrupt() { ... }

    fn disable_interrupt() { ... }

    fn enable() { ... }

    fn disable() { ... }

    fn set_lsb() { ... }

    fn set_msb() { ... }

    fn set_master() { ... }

    fn set_slave() { ... }

    fn enable_double_speed() { ... }

    fn disable_double_speed() { ... }

    fn is_write_collision() -> bool { ... }

    fn send_byte(byte: u8) { ... }

    fn receive_byte() -> u8 { ... }

    fn send_receive(byte: u8) -> u8 { ... }
}

An SPI module.

Information at maxembedded.com.

Associated Types

type MasterInSlaveOut: Pin[src]

type MasterOutSlaveIn: Pin[src]

type Clock: Pin[src]

type SlaveSelect: Pin[src]

type ControlRegister: Register<T = u8>[src]

The SPI control register.

type StatusRegister: Register<T = u8>[src]

The SPI status register.

type DataRegister: Register<T = u8>[src]

The SPI data register.

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Provided methods

fn setup_master(clock: u32)[src]

Sets up the SPI as a master.

fn setup_slave(clock: u32)[src]

Sets up the SPI as a slave.

fn setup_common(clock: u32)[src]

fn set_clock(clock: u32)[src]

Sets the clock speed.

fn enable_interrupt()[src]

Enables interrupts for the spi module.

fn disable_interrupt()[src]

Disables interrupts for the spi module.

fn enable()[src]

Enables the SPI.

fn disable()[src]

Disables the SPI.

fn set_lsb()[src]

Enables least-significant-bit first.

fn set_msb()[src]

Enables most-significant-bit first.

fn set_master()[src]

Enables master mode.

fn set_slave()[src]

Enables slave mode.

fn enable_double_speed()[src]

Enables double speed mode.

fn disable_double_speed()[src]

Disables double speed mode.

fn is_write_collision() -> bool[src]

Checks if there is a write collision.

fn send_byte(byte: u8)[src]

Sends a byte through the serial.

fn receive_byte() -> u8[src]

Reads a byte from the serial.

fn send_receive(byte: u8) -> u8[src]

Sends and receives a byte.

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Implementors

impl HardwareSpi for ruduino::cores::atmega48::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega48a::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega48p::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega48pa::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega88::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega88a::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega88p::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega88pa::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega168::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega168a::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega168p::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega168pa::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega328::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

impl HardwareSpi for ruduino::cores::atmega328p::Spi[src]

type SlaveSelect = B2

type MasterOutSlaveIn = B3

type MasterInSlaveOut = B4

type Clock = B5

type DataRegister = SPDR

type StatusRegister = SPSR

type ControlRegister = SPCR

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