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#![no_std]
#![feature(type_alias_impl_trait)]
extern crate alloc;
use alloc::sync::Arc;
use alloc::vec::Vec;
use core::convert::TryInto;
cfg_if::cfg_if! {
if #[cfg(feature = "async")] {
use core::marker::PhantomData;
use core::pin::Pin;
use core::task::Context;
use core::task::Poll;
use futures_util::sink::Sink;
use futures_util::stream::Stream;
use futures_util::task::AtomicWaker;
}
}
use conquer_once::spin::OnceCell;
use crossbeam_queue::SegQueue;
use spin::RwLock;
use x86_64::instructions::port::Port;
use x86_64::PhysAddr;
use x86_64::VirtAddr;
const RX_BUF_LEN: usize = 8192;
const RX_BUF_WRAP: usize = 1500;
const RX_BUF_PAD: usize = 16;
const RX_BUF_LEN_WRAPPED: usize = RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP;
const APM: u32 = 0b10;
const AB: u32 = 0b1000;
const WRAP: u32 = 0b1000_0000;
const MXDMA_UNLIMITED: u32 = 0b111_0000_0000;
const RXFTH_NONE: u32 = 0b1110_0000_0000_0000;
#[allow(dead_code)]
const RX_BUF_EMPTY: u8 = 0b1;
const TX_ENABLE: u8 = 0b100;
const RX_ENABLE: u8 = 0b1000;
const RST: u8 = 0b10000;
const RX_OK: u16 = 0b1;
const RX_ERR: u16 = 0b10;
const TX_OK: u16 = 0b100;
const TX_ERR: u16 = 0b1000;
const RDU: u16 = 0b10000;
const TDU: u16 = 0b1000_0000;
const SYS_ERR: u16 = 0b1000_0000_0000_0000;
static FRAMES: OnceCell<SegQueue<Vec<u8>>> = OnceCell::uninit();
static RTL8139_STATE: OnceCell<Arc<RwLock<Rtl8139State>>> = OnceCell::uninit();
#[cfg(feature = "async")]
static WAKER: AtomicWaker = AtomicWaker::new();
struct Rtl8139State {
pub config_1: Port<u32>,
pub cmd_reg: Port<u8>,
pub rbstart: Port<u32>,
pub imr: Port<u16>,
pub rcr: Port<u32>,
pub tppoll: Port<u8>,
pub ack: Port<u16>,
pub cpcr: Port<u16>,
pub capr: Port<u16>,
pub idr: [Port<u8>; 6],
pub tx_dat: [Port<u32>; 4],
pub tx_cmd: [Port<u32>; 4],
pub tx_cursor: usize,
pub buffer: [u8; RX_BUF_LEN_WRAPPED],
pub rx_cursor: usize,
pub virt_to_phys: fn(VirtAddr) -> PhysAddr,
}
pub struct RTL8139 {
mac: [u8; 6],
}
impl RTL8139 {
pub fn manifest() -> (u16, u16, u16, u16) {
(0x2, 0x00, 0x10ec, 0x8139)
}
pub unsafe fn preload_unchecked(base: u16, virt_to_phys: fn(VirtAddr) -> PhysAddr) -> Self {
let inner = Rtl8139State {
config_1: Port::new(base + 0x52),
cmd_reg: Port::new(base + 0x37),
rbstart: Port::new(base + 0x30),
imr: Port::new(base + 0x3c),
rcr: Port::new(base + 0x44),
tppoll: Port::new(base + 0xd9),
ack: Port::new(base + 0x3e),
cpcr: Port::new(base + 0xe0),
capr: Port::new(base + 0x38),
idr: [
Port::new(base + 0x00),
Port::new(base + 0x01),
Port::new(base + 0x02),
Port::new(base + 0x03),
Port::new(base + 0x04),
Port::new(base + 0x05),
],
tx_dat: [
Port::new(base + 0x20),
Port::new(base + 0x24),
Port::new(base + 0x28),
Port::new(base + 0x2c),
],
tx_cmd: [
Port::new(base + 0x10),
Port::new(base + 0x14),
Port::new(base + 0x18),
Port::new(base + 0x1c),
],
tx_cursor: 0,
buffer: [0u8; RX_BUF_LEN_WRAPPED],
rx_cursor: 0,
virt_to_phys,
};
FRAMES.init_once(|| SegQueue::new());
RTL8139_STATE.init_once(move || Arc::new(RwLock::new(inner)));
Self {
mac: [0xff, 0xff, 0xff, 0xff, 0xff, 0xff],
}
}
pub fn load(&mut self) -> Result<(), ()> {
let mut inner = RTL8139_STATE.try_get().unwrap().write();
unsafe {
inner.config_1.write(0x0);
inner.cmd_reg.write(RST);
}
loop {
if (unsafe { inner.cmd_reg.read() } & 0x10) == 0 {
break;
}
}
let raw_mac = inner
.idr
.iter_mut()
.map(|x| unsafe { x.read() })
.collect::<Vec<u8>>();
self.mac = raw_mac
.as_slice()
.try_into()
.expect("rtl8139: failed to read mac");
let buffer_virt = unsafe { VirtAddr::new_unsafe(inner.buffer.as_ptr() as u64) };
let virt_to_phys = &inner.virt_to_phys;
let buffer_ptr = virt_to_phys(buffer_virt).as_u64() as u32;
unsafe {
inner
.rcr
.write(APM | AB | MXDMA_UNLIMITED | RXFTH_NONE | WRAP);
inner.cmd_reg.write(RX_ENABLE | TX_ENABLE);
inner.rbstart.write(buffer_ptr);
}
unsafe {
inner.cmd_reg.write(RX_ENABLE | TX_ENABLE);
inner
.imr
.write(0xffff | RX_OK | TX_OK | RX_ERR | TX_ERR | SYS_ERR | RDU | TDU);
}
Ok(())
}
pub fn on_interrupt() {
let mut inner = RTL8139_STATE.try_get().unwrap().write();
let isr = unsafe { inner.ack.read() };
if (isr & RX_OK) != 0 {
while (unsafe { inner.cmd_reg.read() } & RX_BUF_EMPTY) == 0 {
FRAMES.try_get().unwrap().push(inner.rok());
#[cfg(feature = "async")]
WAKER.wake();
}
}
unsafe {
inner.ack.write(isr);
}
}
pub fn try_recv(&mut self) -> Option<Vec<u8>> {
FRAMES.try_get().unwrap().pop()
}
pub fn send(&mut self, buffer: &[u8]) {
x86_64::instructions::interrupts::disable();
{
if let Some(mut lock) = RTL8139_STATE
.try_get()
.expect("rtl8139: state not init")
.try_write()
{
unsafe { lock.write(buffer) };
};
}
x86_64::instructions::interrupts::enable();
}
pub fn mac(&self) -> [u8; 6] {
self.mac
}
#[cfg(feature = "async")]
pub fn parts(&mut self) -> (RxSink, TxSink) {
(RxSink::new(), TxSink::new())
}
}
impl Rtl8139State {
fn rok(&mut self) -> Vec<u8> {
let buffer = &self.buffer[self.rx_cursor..];
let length = u16::from_le_bytes(buffer[2..4].try_into().expect("Got wrong len")) as usize;
assert!(
length >= 64,
"rtl8139: ROK Len is less than 64. THIS IS A BUG."
);
let frame = buffer[4..length].to_vec();
self.rx_cursor = (self.rx_cursor + length as usize + 4 + 3) & !3;
if self.rx_cursor > RX_BUF_LEN {
self.rx_cursor -= RX_BUF_LEN
}
unsafe {
self.capr.write((self.rx_cursor - 0x10) as u16);
}
frame
}
pub unsafe fn write(&mut self, data: &[u8]) {
let virt_to_phys = &self.virt_to_phys;
let cursor = self.tx_cursor;
let data_ptr = virt_to_phys(VirtAddr::new_unsafe(data.as_ptr() as u64)).as_u64();
self.tx_dat[cursor].write(data_ptr as u32);
self.tx_cmd[cursor].write((data.len() as u32) & 0xfff);
loop {
if (self.tx_cmd[cursor].read() & 0x8000) != 0 {
break;
}
}
self.tx_cursor = (cursor + 1) % 4;
}
}
#[cfg(feature = "async")]
pub struct RxSink {
_private: PhantomData<()>,
}
#[cfg(feature = "async")]
impl RxSink {
fn new() -> Self {
Self {
_private: PhantomData,
}
}
}
#[cfg(feature = "async")]
impl Stream for RxSink {
type Item = Vec<u8>;
fn poll_next(self: Pin<&mut Self>, cx: &mut Context) -> Poll<Option<Self::Item>> {
if let Some(x) = FRAMES.try_get().unwrap().pop() {
return Poll::Ready(Some(x));
}
WAKER.register(&cx.waker());
match FRAMES.try_get().unwrap().pop() {
Some(x) => {
WAKER.take();
Poll::Ready(Some(x))
}
None => Poll::Pending,
}
}
}
#[cfg(feature = "async")]
pub struct TxSink {
buffer: Vec<Vec<u8>>,
}
#[cfg(feature = "async")]
impl TxSink {
fn new() -> Self {
Self { buffer: Vec::new() }
}
}
#[cfg(feature = "async")]
impl Sink<Vec<u8>> for TxSink {
type Error = ();
fn poll_ready(self: Pin<&mut Self>, _: &mut Context<'_>) -> Poll<Result<(), Self::Error>> {
Poll::Ready(Ok(()))
}
fn start_send(mut self: Pin<&mut Self>, item: Vec<u8>) -> Result<(), Self::Error> {
self.buffer.push(item);
Ok(())
}
fn poll_flush(mut self: Pin<&mut Self>, _: &mut Context<'_>) -> Poll<Result<(), Self::Error>> {
x86_64::instructions::interrupts::disable();
{
let mut lock = if let Some(x) = RTL8139_STATE
.try_get()
.expect("rtl8139: state not init")
.try_write()
{
x
} else {
return Poll::Pending;
};
for item in self.buffer.drain(..) {
unsafe { lock.write(&item) };
}
}
x86_64::instructions::interrupts::enable();
Poll::Ready(Ok(()))
}
fn poll_close(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<(), Self::Error>> {
self.poll_flush(cx)
}
}