Type Definition rsl10_pac::rf::rf_reg28::W

type W = W<u32, RF_REG28>;

Writer for register RF_REG28

Methods

impl W

pub fn ctrl_rx_switch_lp(&mut self) -> CTRL_RX_SWITCH_LP_W

Bit 31 - If set to 1 switch the low-pass filter in the Rx chain

pub fn ctrl_rx_use_peak_detector(&mut self) -> CTRL_RX_USE_PEAK_DETECTOR_W

Bit 30 - If set to 1, the peak detector is powered on during the Rx by the FSM

pub fn ctrl_rx_start_mix_on_cal(&mut self) -> CTRL_RX_START_MIX_ON_CAL_W

Bit 29 - If set to 1, the mixer is enabled during the sub-band selection phase

pub fn ctrl_rx_ctrl_rx(&mut self) -> CTRL_RX_CTRL_RX_W

Bits 24:28 - bits(1:0) => resonance 1 LNA, bits(3:2) => resonance 2 LNA, bit(4) => IFA PTAT-R only

pub fn swcap_fsm_sb_cap_rx(&mut self) -> SWCAP_FSM_SB_CAP_RX_W

Bits 20:23 - VCO subband selection (Rx in FSM mode)

pub fn swcap_fsm_sb_cap_tx(&mut self) -> SWCAP_FSM_SB_CAP_TX_W

Bits 16:19 - VCO subband selection (Tx in FSM mode)

pub fn dll_ctrl_ck_last_sel_delay(&mut self) -> DLL_CTRL_CK_LAST_SEL_DELAY_W

Bit 10

pub fn dll_ctrl_ck_first_sel_delay(&mut self) -> DLL_CTRL_CK_FIRST_SEL_DELAY_W

Bit 9

pub fn dll_ctrl_ck_ext_sel(&mut self) -> DLL_CTRL_CK_EXT_SEL_W

Bit 8 - Low: input clock comes from ck_xtal pin (default). High: input clock comes from ck_ext pin

pub fn dll_ctrl_ck_dig_en(&mut self) -> DLL_CTRL_CK_DIG_EN_W

Bit 7 - Debug: enable to use the alternate ck_dig pin to output the PLL reference clock signal

pub fn dll_ctrl_ck_test_en(&mut self) -> DLL_CTRL_CK_TEST_EN_W

Bit 6 - Debug: enable to output on GPIO the PLL reference clock signal via ck_test pin

pub fn dll_ctrl_too_fast_enb(&mut self) -> DLL_CTRL_TOO_FAST_ENB_W

Bit 5 - When low, enable auxiliary wide lock range phase detector when fast mode locking is enabled (fast_enb = 0). When high, only the narrow lock range phase detector is enabled and bit 2 (fast_enb) must be high to avoid false frequency lock (slow mode locking)

pub fn dll_ctrl_locked_det_en(&mut self) -> DLL_CTRL_LOCKED_DET_EN_W

Bit 4 - Enable reference frequency multiplier locked detector. When this signal is high, the dll_locked output goes high when the output multiplied clock is nearly about three times the frequency of the input clock.

pub fn dll_ctrl_locked_auto_check_en(
    &mut self
) -> DLL_CTRL_LOCKED_AUTO_CHECK_EN_W

Bit 3 - If for some reason the reference frequency multiplier is out of lock (usually because some input clocks from ck_xtal or ck_ext are missing) and this signal is high, the frequency multiplier will try to lock again automatically. Otherwise, a manual reset should be performed via dll_rstb input(see Table 3) to relock the frequency multiplier. This mode only works if bit 4 is also high (locked detector enabled, see below)

pub fn dll_ctrl_fast_enb(&mut self) -> DLL_CTRL_FAST_ENB_W

Bit 2 - Enable, when low, fast mode locking of the reference frequency multiplier (default). Bit 5 must also be set low in this mode of operation (see below)

pub fn dll_ctrl_ck_sel(&mut self) -> DLL_CTRL_CK_SEL_W

Bits 0:1 - Selection of the clock used as frequency reference of the PLL (also to ck_test and ck_dig outputs): 00 => ref = ck_xtal ot ck_ext (if bit 8 is high), 01 => ref = same as ck_sel = 00 if dll_en = 0, otherwise frequency(ref) = 3x frequency(ck_xtal) or 3x frequency(ck_ext) (if bit 8 is high), 10 => ref = same as ck_sel = 01 but output frequency divided by 2 (used in normal RX mode when dll_en = 0), 11 => ref = same as ck_sel = 01 but output frequency divided by 5 (used for RX mode with external signal at 132 MHz when dll_en = 0)