#[repr(C)]
pub struct __BindgenUnionField<T>(::core::marker::PhantomData<T>);
impl<T> __BindgenUnionField<T> {
#[inline]
pub const fn new() -> Self {
__BindgenUnionField(::core::marker::PhantomData)
}
#[inline]
pub unsafe fn as_ref(&self) -> &T {
::core::mem::transmute(self)
}
#[inline]
pub unsafe fn as_mut(&mut self) -> &mut T {
::core::mem::transmute(self)
}
}
impl<T> ::core::default::Default for __BindgenUnionField<T> {
#[inline]
fn default() -> Self {
Self::new()
}
}
impl<T> ::core::clone::Clone for __BindgenUnionField<T> {
#[inline]
fn clone(&self) -> Self {
Self::new()
}
}
impl<T> ::core::marker::Copy for __BindgenUnionField<T> {}
impl<T> ::core::fmt::Debug for __BindgenUnionField<T> {
fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
fmt.write_str("__BindgenUnionField")
}
}
impl<T> ::core::hash::Hash for __BindgenUnionField<T> {
fn hash<H: ::core::hash::Hasher>(&self, _state: &mut H) {}
}
impl<T> ::core::cmp::PartialEq for __BindgenUnionField<T> {
fn eq(&self, _other: &__BindgenUnionField<T>) -> bool {
true
}
}
impl<T> ::core::cmp::Eq for __BindgenUnionField<T> {}
pub const PICO_DEFAULT_UART: u32 = 0;
pub const PICO_DEFAULT_UART_TX_PIN: u32 = 0;
pub const PICO_DEFAULT_UART_RX_PIN: u32 = 1;
pub const PICO_DEFAULT_LED_PIN: u32 = 25;
pub const PICO_FLASH_SPI_CLKDIV: u32 = 2;
pub const PICO_FLASH_SIZE_BYTES: u32 = 2097152;
pub const PICO_SMPS_MODE_PIN: u32 = 23;
pub const PICO_FLOAT_SUPPORT_ROM_V1: u32 = 1;
pub const PICO_DOUBLE_SUPPORT_ROM_V1: u32 = 1;
pub const __WORDSIZE: u32 = 64;
pub const __DARWIN_ONLY_64_BIT_INO_T: u32 = 0;
pub const __DARWIN_ONLY_UNIX_CONFORMANCE: u32 = 1;
pub const __DARWIN_ONLY_VERS_1050: u32 = 0;
pub const __DARWIN_UNIX03: u32 = 1;
pub const __DARWIN_64_BIT_INO_T: u32 = 1;
pub const __DARWIN_VERS_1050: u32 = 1;
pub const __DARWIN_NON_CANCELABLE: u32 = 0;
pub const __DARWIN_SUF_64_BIT_INO_T: &'static [u8; 9usize] = b"$INODE64\0";
pub const __DARWIN_SUF_1050: &'static [u8; 6usize] = b"$1050\0";
pub const __DARWIN_SUF_EXTSN: &'static [u8; 14usize] = b"$DARWIN_EXTSN\0";
pub const __DARWIN_C_ANSI: u32 = 4096;
pub const __DARWIN_C_FULL: u32 = 900000;
pub const __DARWIN_C_LEVEL: u32 = 900000;
pub const __STDC_WANT_LIB_EXT1__: u32 = 1;
pub const __DARWIN_NO_LONG_LONG: u32 = 0;
pub const _DARWIN_FEATURE_64_BIT_INODE: u32 = 1;
pub const _DARWIN_FEATURE_ONLY_UNIX_CONFORMANCE: u32 = 1;
pub const _DARWIN_FEATURE_UNIX_CONFORMANCE: u32 = 3;
pub const __PTHREAD_SIZE__: u32 = 8176;
pub const __PTHREAD_ATTR_SIZE__: u32 = 56;
pub const __PTHREAD_MUTEXATTR_SIZE__: u32 = 8;
pub const __PTHREAD_MUTEX_SIZE__: u32 = 56;
pub const __PTHREAD_CONDATTR_SIZE__: u32 = 8;
pub const __PTHREAD_COND_SIZE__: u32 = 40;
pub const __PTHREAD_ONCE_SIZE__: u32 = 8;
pub const __PTHREAD_RWLOCK_SIZE__: u32 = 192;
pub const __PTHREAD_RWLOCKATTR_SIZE__: u32 = 16;
pub const INT8_MAX: u32 = 127;
pub const INT16_MAX: u32 = 32767;
pub const INT32_MAX: u32 = 2147483647;
pub const INT64_MAX: u64 = 9223372036854775807;
pub const INT8_MIN: i32 = -128;
pub const INT16_MIN: i32 = -32768;
pub const INT32_MIN: i32 = -2147483648;
pub const INT64_MIN: i64 = -9223372036854775808;
pub const UINT8_MAX: u32 = 255;
pub const UINT16_MAX: u32 = 65535;
pub const UINT32_MAX: u32 = 4294967295;
pub const UINT64_MAX: i32 = -1;
pub const INT_LEAST8_MIN: i32 = -128;
pub const INT_LEAST16_MIN: i32 = -32768;
pub const INT_LEAST32_MIN: i32 = -2147483648;
pub const INT_LEAST64_MIN: i64 = -9223372036854775808;
pub const INT_LEAST8_MAX: u32 = 127;
pub const INT_LEAST16_MAX: u32 = 32767;
pub const INT_LEAST32_MAX: u32 = 2147483647;
pub const INT_LEAST64_MAX: u64 = 9223372036854775807;
pub const UINT_LEAST8_MAX: u32 = 255;
pub const UINT_LEAST16_MAX: u32 = 65535;
pub const UINT_LEAST32_MAX: u32 = 4294967295;
pub const UINT_LEAST64_MAX: i32 = -1;
pub const INT_FAST8_MIN: i32 = -128;
pub const INT_FAST16_MIN: i32 = -32768;
pub const INT_FAST32_MIN: i32 = -2147483648;
pub const INT_FAST64_MIN: i64 = -9223372036854775808;
pub const INT_FAST8_MAX: u32 = 127;
pub const INT_FAST16_MAX: u32 = 32767;
pub const INT_FAST32_MAX: u32 = 2147483647;
pub const INT_FAST64_MAX: u64 = 9223372036854775807;
pub const UINT_FAST8_MAX: u32 = 255;
pub const UINT_FAST16_MAX: u32 = 65535;
pub const UINT_FAST32_MAX: u32 = 4294967295;
pub const UINT_FAST64_MAX: i32 = -1;
pub const INTPTR_MAX: u64 = 9223372036854775807;
pub const INTPTR_MIN: i64 = -9223372036854775808;
pub const UINTPTR_MAX: i32 = -1;
pub const SIZE_MAX: i32 = -1;
pub const RSIZE_MAX: i32 = -1;
pub const WINT_MIN: i32 = -2147483648;
pub const WINT_MAX: u32 = 2147483647;
pub const SIG_ATOMIC_MIN: i32 = -2147483648;
pub const SIG_ATOMIC_MAX: u32 = 2147483647;
pub const true_: u32 = 1;
pub const false_: u32 = 0;
pub const __bool_true_false_are_defined: u32 = 1;
pub const PICO_SDK_VERSION_MAJOR: u32 = 1;
pub const PICO_SDK_VERSION_MINOR: u32 = 0;
pub const PICO_SDK_VERSION_REVISION: u32 = 0;
pub const PICO_SDK_VERSION_STRING: &'static [u8; 6usize] = b"1.0.0\0";
pub const REG_ALIAS_RW_BITS: u32 = 0;
pub const REG_ALIAS_XOR_BITS: u32 = 4096;
pub const REG_ALIAS_SET_BITS: u32 = 8192;
pub const REG_ALIAS_CLR_BITS: u32 = 12288;
pub const ROM_BASE: u32 = 0;
pub const XIP_BASE: u32 = 268435456;
pub const XIP_MAIN_BASE: u32 = 268435456;
pub const XIP_NOALLOC_BASE: u32 = 285212672;
pub const XIP_NOCACHE_BASE: u32 = 301989888;
pub const XIP_NOCACHE_NOALLOC_BASE: u32 = 318767104;
pub const XIP_CTRL_BASE: u32 = 335544320;
pub const XIP_SRAM_BASE: u32 = 352321536;
pub const XIP_SRAM_END: u32 = 352337920;
pub const XIP_SSI_BASE: u32 = 402653184;
pub const SRAM_BASE: u32 = 536870912;
pub const SRAM_STRIPED_BASE: u32 = 536870912;
pub const SRAM_STRIPED_END: u32 = 537133056;
pub const SRAM4_BASE: u32 = 537133056;
pub const SRAM5_BASE: u32 = 537137152;
pub const SRAM_END: u32 = 537141248;
pub const SRAM0_BASE: u32 = 553648128;
pub const SRAM1_BASE: u32 = 553713664;
pub const SRAM2_BASE: u32 = 553779200;
pub const SRAM3_BASE: u32 = 553844736;
pub const SYSINFO_BASE: u32 = 1073741824;
pub const SYSCFG_BASE: u32 = 1073758208;
pub const CLOCKS_BASE: u32 = 1073774592;
pub const RESETS_BASE: u32 = 1073790976;
pub const PSM_BASE: u32 = 1073807360;
pub const IO_BANK0_BASE: u32 = 1073823744;
pub const IO_QSPI_BASE: u32 = 1073840128;
pub const PADS_BANK0_BASE: u32 = 1073856512;
pub const PADS_QSPI_BASE: u32 = 1073872896;
pub const XOSC_BASE: u32 = 1073889280;
pub const PLL_SYS_BASE: u32 = 1073905664;
pub const PLL_USB_BASE: u32 = 1073922048;
pub const BUSCTRL_BASE: u32 = 1073938432;
pub const UART0_BASE: u32 = 1073954816;
pub const UART1_BASE: u32 = 1073971200;
pub const SPI0_BASE: u32 = 1073987584;
pub const SPI1_BASE: u32 = 1074003968;
pub const I2C0_BASE: u32 = 1074020352;
pub const I2C1_BASE: u32 = 1074036736;
pub const ADC_BASE: u32 = 1074053120;
pub const PWM_BASE: u32 = 1074069504;
pub const TIMER_BASE: u32 = 1074085888;
pub const WATCHDOG_BASE: u32 = 1074102272;
pub const RTC_BASE: u32 = 1074118656;
pub const ROSC_BASE: u32 = 1074135040;
pub const VREG_AND_CHIP_RESET_BASE: u32 = 1074151424;
pub const TBMAN_BASE: u32 = 1074184192;
pub const DMA_BASE: u32 = 1342177280;
pub const USBCTRL_DPRAM_BASE: u32 = 1343225856;
pub const USBCTRL_BASE: u32 = 1343225856;
pub const USBCTRL_REGS_BASE: u32 = 1343291392;
pub const PIO0_BASE: u32 = 1344274432;
pub const PIO1_BASE: u32 = 1345323008;
pub const XIP_AUX_BASE: u32 = 1346371584;
pub const SIO_BASE: u32 = 3489660928;
pub const PPB_BASE: u32 = 3758096384;
pub const NUM_CORES: u32 = 2;
pub const NUM_DMA_CHANNELS: u32 = 12;
pub const NUM_IRQS: u32 = 32;
pub const NUM_PIOS: u32 = 2;
pub const NUM_PIO_STATE_MACHINES: u32 = 4;
pub const NUM_PWM_SLICES: u32 = 8;
pub const NUM_SPIN_LOCKS: u32 = 32;
pub const NUM_UARTS: u32 = 2;
pub const NUM_BANK0_GPIOS: u32 = 30;
pub const PIO_INSTRUCTION_COUNT: u32 = 32;
pub const XOSC_MHZ: u32 = 12;
pub const PICO_STACK_SIZE: u32 = 2048;
pub const PICO_HEAP_SIZE: u32 = 2048;
pub const PICO_NO_RAM_VECTOR_TABLE: u32 = 0;
pub const PARAM_ASSERTIONS_ENABLE_ALL: u32 = 0;
pub const PARAM_ASSERTIONS_DISABLE_ALL: u32 = 0;
pub const PICO_STDOUT_MUTEX: u32 = 1;
pub const PICO_STDIO_ENABLE_CRLF_SUPPORT: u32 = 1;
pub const PICO_STDIO_DEFAULT_CRLF: u32 = 1;
pub const PICO_STDIO_STACK_BUFFER_SIZE: u32 = 128;
pub const TIMER_TIMEHW_OFFSET: u32 = 0;
pub const TIMER_TIMEHW_BITS: u32 = 4294967295;
pub const TIMER_TIMEHW_RESET: u32 = 0;
pub const TIMER_TIMEHW_MSB: u32 = 31;
pub const TIMER_TIMEHW_LSB: u32 = 0;
pub const TIMER_TIMEHW_ACCESS: &'static [u8; 3usize] = b"WF\0";
pub const TIMER_TIMELW_OFFSET: u32 = 4;
pub const TIMER_TIMELW_BITS: u32 = 4294967295;
pub const TIMER_TIMELW_RESET: u32 = 0;
pub const TIMER_TIMELW_MSB: u32 = 31;
pub const TIMER_TIMELW_LSB: u32 = 0;
pub const TIMER_TIMELW_ACCESS: &'static [u8; 3usize] = b"WF\0";
pub const TIMER_TIMEHR_OFFSET: u32 = 8;
pub const TIMER_TIMEHR_BITS: u32 = 4294967295;
pub const TIMER_TIMEHR_RESET: u32 = 0;
pub const TIMER_TIMEHR_MSB: u32 = 31;
pub const TIMER_TIMEHR_LSB: u32 = 0;
pub const TIMER_TIMEHR_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_TIMELR_OFFSET: u32 = 12;
pub const TIMER_TIMELR_BITS: u32 = 4294967295;
pub const TIMER_TIMELR_RESET: u32 = 0;
pub const TIMER_TIMELR_MSB: u32 = 31;
pub const TIMER_TIMELR_LSB: u32 = 0;
pub const TIMER_TIMELR_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_ALARM0_OFFSET: u32 = 16;
pub const TIMER_ALARM0_BITS: u32 = 4294967295;
pub const TIMER_ALARM0_RESET: u32 = 0;
pub const TIMER_ALARM0_MSB: u32 = 31;
pub const TIMER_ALARM0_LSB: u32 = 0;
pub const TIMER_ALARM0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_ALARM1_OFFSET: u32 = 20;
pub const TIMER_ALARM1_BITS: u32 = 4294967295;
pub const TIMER_ALARM1_RESET: u32 = 0;
pub const TIMER_ALARM1_MSB: u32 = 31;
pub const TIMER_ALARM1_LSB: u32 = 0;
pub const TIMER_ALARM1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_ALARM2_OFFSET: u32 = 24;
pub const TIMER_ALARM2_BITS: u32 = 4294967295;
pub const TIMER_ALARM2_RESET: u32 = 0;
pub const TIMER_ALARM2_MSB: u32 = 31;
pub const TIMER_ALARM2_LSB: u32 = 0;
pub const TIMER_ALARM2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_ALARM3_OFFSET: u32 = 28;
pub const TIMER_ALARM3_BITS: u32 = 4294967295;
pub const TIMER_ALARM3_RESET: u32 = 0;
pub const TIMER_ALARM3_MSB: u32 = 31;
pub const TIMER_ALARM3_LSB: u32 = 0;
pub const TIMER_ALARM3_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_ARMED_OFFSET: u32 = 32;
pub const TIMER_ARMED_BITS: u32 = 15;
pub const TIMER_ARMED_RESET: u32 = 0;
pub const TIMER_ARMED_MSB: u32 = 3;
pub const TIMER_ARMED_LSB: u32 = 0;
pub const TIMER_ARMED_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const TIMER_TIMERAWH_OFFSET: u32 = 36;
pub const TIMER_TIMERAWH_BITS: u32 = 4294967295;
pub const TIMER_TIMERAWH_RESET: u32 = 0;
pub const TIMER_TIMERAWH_MSB: u32 = 31;
pub const TIMER_TIMERAWH_LSB: u32 = 0;
pub const TIMER_TIMERAWH_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_TIMERAWL_OFFSET: u32 = 40;
pub const TIMER_TIMERAWL_BITS: u32 = 4294967295;
pub const TIMER_TIMERAWL_RESET: u32 = 0;
pub const TIMER_TIMERAWL_MSB: u32 = 31;
pub const TIMER_TIMERAWL_LSB: u32 = 0;
pub const TIMER_TIMERAWL_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_DBGPAUSE_OFFSET: u32 = 44;
pub const TIMER_DBGPAUSE_BITS: u32 = 6;
pub const TIMER_DBGPAUSE_RESET: u32 = 7;
pub const TIMER_DBGPAUSE_DBG1_RESET: u32 = 1;
pub const TIMER_DBGPAUSE_DBG1_BITS: u32 = 4;
pub const TIMER_DBGPAUSE_DBG1_MSB: u32 = 2;
pub const TIMER_DBGPAUSE_DBG1_LSB: u32 = 2;
pub const TIMER_DBGPAUSE_DBG1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_DBGPAUSE_DBG0_RESET: u32 = 1;
pub const TIMER_DBGPAUSE_DBG0_BITS: u32 = 2;
pub const TIMER_DBGPAUSE_DBG0_MSB: u32 = 1;
pub const TIMER_DBGPAUSE_DBG0_LSB: u32 = 1;
pub const TIMER_DBGPAUSE_DBG0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_PAUSE_OFFSET: u32 = 48;
pub const TIMER_PAUSE_BITS: u32 = 1;
pub const TIMER_PAUSE_RESET: u32 = 0;
pub const TIMER_PAUSE_MSB: u32 = 0;
pub const TIMER_PAUSE_LSB: u32 = 0;
pub const TIMER_PAUSE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTR_OFFSET: u32 = 52;
pub const TIMER_INTR_BITS: u32 = 15;
pub const TIMER_INTR_RESET: u32 = 0;
pub const TIMER_INTR_ALARM_3_RESET: u32 = 0;
pub const TIMER_INTR_ALARM_3_BITS: u32 = 8;
pub const TIMER_INTR_ALARM_3_MSB: u32 = 3;
pub const TIMER_INTR_ALARM_3_LSB: u32 = 3;
pub const TIMER_INTR_ALARM_3_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const TIMER_INTR_ALARM_2_RESET: u32 = 0;
pub const TIMER_INTR_ALARM_2_BITS: u32 = 4;
pub const TIMER_INTR_ALARM_2_MSB: u32 = 2;
pub const TIMER_INTR_ALARM_2_LSB: u32 = 2;
pub const TIMER_INTR_ALARM_2_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const TIMER_INTR_ALARM_1_RESET: u32 = 0;
pub const TIMER_INTR_ALARM_1_BITS: u32 = 2;
pub const TIMER_INTR_ALARM_1_MSB: u32 = 1;
pub const TIMER_INTR_ALARM_1_LSB: u32 = 1;
pub const TIMER_INTR_ALARM_1_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const TIMER_INTR_ALARM_0_RESET: u32 = 0;
pub const TIMER_INTR_ALARM_0_BITS: u32 = 1;
pub const TIMER_INTR_ALARM_0_MSB: u32 = 0;
pub const TIMER_INTR_ALARM_0_LSB: u32 = 0;
pub const TIMER_INTR_ALARM_0_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const TIMER_INTE_OFFSET: u32 = 56;
pub const TIMER_INTE_BITS: u32 = 15;
pub const TIMER_INTE_RESET: u32 = 0;
pub const TIMER_INTE_ALARM_3_RESET: u32 = 0;
pub const TIMER_INTE_ALARM_3_BITS: u32 = 8;
pub const TIMER_INTE_ALARM_3_MSB: u32 = 3;
pub const TIMER_INTE_ALARM_3_LSB: u32 = 3;
pub const TIMER_INTE_ALARM_3_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTE_ALARM_2_RESET: u32 = 0;
pub const TIMER_INTE_ALARM_2_BITS: u32 = 4;
pub const TIMER_INTE_ALARM_2_MSB: u32 = 2;
pub const TIMER_INTE_ALARM_2_LSB: u32 = 2;
pub const TIMER_INTE_ALARM_2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTE_ALARM_1_RESET: u32 = 0;
pub const TIMER_INTE_ALARM_1_BITS: u32 = 2;
pub const TIMER_INTE_ALARM_1_MSB: u32 = 1;
pub const TIMER_INTE_ALARM_1_LSB: u32 = 1;
pub const TIMER_INTE_ALARM_1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTE_ALARM_0_RESET: u32 = 0;
pub const TIMER_INTE_ALARM_0_BITS: u32 = 1;
pub const TIMER_INTE_ALARM_0_MSB: u32 = 0;
pub const TIMER_INTE_ALARM_0_LSB: u32 = 0;
pub const TIMER_INTE_ALARM_0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTF_OFFSET: u32 = 60;
pub const TIMER_INTF_BITS: u32 = 15;
pub const TIMER_INTF_RESET: u32 = 0;
pub const TIMER_INTF_ALARM_3_RESET: u32 = 0;
pub const TIMER_INTF_ALARM_3_BITS: u32 = 8;
pub const TIMER_INTF_ALARM_3_MSB: u32 = 3;
pub const TIMER_INTF_ALARM_3_LSB: u32 = 3;
pub const TIMER_INTF_ALARM_3_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTF_ALARM_2_RESET: u32 = 0;
pub const TIMER_INTF_ALARM_2_BITS: u32 = 4;
pub const TIMER_INTF_ALARM_2_MSB: u32 = 2;
pub const TIMER_INTF_ALARM_2_LSB: u32 = 2;
pub const TIMER_INTF_ALARM_2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTF_ALARM_1_RESET: u32 = 0;
pub const TIMER_INTF_ALARM_1_BITS: u32 = 2;
pub const TIMER_INTF_ALARM_1_MSB: u32 = 1;
pub const TIMER_INTF_ALARM_1_LSB: u32 = 1;
pub const TIMER_INTF_ALARM_1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTF_ALARM_0_RESET: u32 = 0;
pub const TIMER_INTF_ALARM_0_BITS: u32 = 1;
pub const TIMER_INTF_ALARM_0_MSB: u32 = 0;
pub const TIMER_INTF_ALARM_0_LSB: u32 = 0;
pub const TIMER_INTF_ALARM_0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const TIMER_INTS_OFFSET: u32 = 64;
pub const TIMER_INTS_BITS: u32 = 15;
pub const TIMER_INTS_RESET: u32 = 0;
pub const TIMER_INTS_ALARM_3_RESET: u32 = 0;
pub const TIMER_INTS_ALARM_3_BITS: u32 = 8;
pub const TIMER_INTS_ALARM_3_MSB: u32 = 3;
pub const TIMER_INTS_ALARM_3_LSB: u32 = 3;
pub const TIMER_INTS_ALARM_3_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_INTS_ALARM_2_RESET: u32 = 0;
pub const TIMER_INTS_ALARM_2_BITS: u32 = 4;
pub const TIMER_INTS_ALARM_2_MSB: u32 = 2;
pub const TIMER_INTS_ALARM_2_LSB: u32 = 2;
pub const TIMER_INTS_ALARM_2_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_INTS_ALARM_1_RESET: u32 = 0;
pub const TIMER_INTS_ALARM_1_BITS: u32 = 2;
pub const TIMER_INTS_ALARM_1_MSB: u32 = 1;
pub const TIMER_INTS_ALARM_1_LSB: u32 = 1;
pub const TIMER_INTS_ALARM_1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const TIMER_INTS_ALARM_0_RESET: u32 = 0;
pub const TIMER_INTS_ALARM_0_BITS: u32 = 1;
pub const TIMER_INTS_ALARM_0_MSB: u32 = 0;
pub const TIMER_INTS_ALARM_0_LSB: u32 = 0;
pub const TIMER_INTS_ALARM_0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const NUM_TIMERS: u32 = 4;
pub const PARAM_ASSERTIONS_ENABLED_TIMER: u32 = 0;
pub const PARAM_ASSERTIONS_ENABLED_TIME: u32 = 0;
pub const PICO_TIME_SLEEP_OVERHEAD_ADJUST_US: u32 = 6;
pub const PICO_TIME_DEFAULT_ALARM_POOL_DISABLED: u32 = 0;
pub const PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM: u32 = 3;
pub const PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS: u32 = 16;
pub const SIO_CPUID_OFFSET: u32 = 0;
pub const SIO_CPUID_BITS: u32 = 4294967295;
pub const SIO_CPUID_RESET: &'static [u8; 2usize] = b"-\0";
pub const SIO_CPUID_MSB: u32 = 31;
pub const SIO_CPUID_LSB: u32 = 0;
pub const SIO_CPUID_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_GPIO_IN_OFFSET: u32 = 4;
pub const SIO_GPIO_IN_BITS: u32 = 1073741823;
pub const SIO_GPIO_IN_RESET: u32 = 0;
pub const SIO_GPIO_IN_MSB: u32 = 29;
pub const SIO_GPIO_IN_LSB: u32 = 0;
pub const SIO_GPIO_IN_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_GPIO_HI_IN_OFFSET: u32 = 8;
pub const SIO_GPIO_HI_IN_BITS: u32 = 63;
pub const SIO_GPIO_HI_IN_RESET: u32 = 0;
pub const SIO_GPIO_HI_IN_MSB: u32 = 5;
pub const SIO_GPIO_HI_IN_LSB: u32 = 0;
pub const SIO_GPIO_HI_IN_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_GPIO_OUT_OFFSET: u32 = 16;
pub const SIO_GPIO_OUT_BITS: u32 = 1073741823;
pub const SIO_GPIO_OUT_RESET: u32 = 0;
pub const SIO_GPIO_OUT_MSB: u32 = 29;
pub const SIO_GPIO_OUT_LSB: u32 = 0;
pub const SIO_GPIO_OUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OUT_SET_OFFSET: u32 = 20;
pub const SIO_GPIO_OUT_SET_BITS: u32 = 1073741823;
pub const SIO_GPIO_OUT_SET_RESET: u32 = 0;
pub const SIO_GPIO_OUT_SET_MSB: u32 = 29;
pub const SIO_GPIO_OUT_SET_LSB: u32 = 0;
pub const SIO_GPIO_OUT_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OUT_CLR_OFFSET: u32 = 24;
pub const SIO_GPIO_OUT_CLR_BITS: u32 = 1073741823;
pub const SIO_GPIO_OUT_CLR_RESET: u32 = 0;
pub const SIO_GPIO_OUT_CLR_MSB: u32 = 29;
pub const SIO_GPIO_OUT_CLR_LSB: u32 = 0;
pub const SIO_GPIO_OUT_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OUT_XOR_OFFSET: u32 = 28;
pub const SIO_GPIO_OUT_XOR_BITS: u32 = 1073741823;
pub const SIO_GPIO_OUT_XOR_RESET: u32 = 0;
pub const SIO_GPIO_OUT_XOR_MSB: u32 = 29;
pub const SIO_GPIO_OUT_XOR_LSB: u32 = 0;
pub const SIO_GPIO_OUT_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OE_OFFSET: u32 = 32;
pub const SIO_GPIO_OE_BITS: u32 = 1073741823;
pub const SIO_GPIO_OE_RESET: u32 = 0;
pub const SIO_GPIO_OE_MSB: u32 = 29;
pub const SIO_GPIO_OE_LSB: u32 = 0;
pub const SIO_GPIO_OE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OE_SET_OFFSET: u32 = 36;
pub const SIO_GPIO_OE_SET_BITS: u32 = 1073741823;
pub const SIO_GPIO_OE_SET_RESET: u32 = 0;
pub const SIO_GPIO_OE_SET_MSB: u32 = 29;
pub const SIO_GPIO_OE_SET_LSB: u32 = 0;
pub const SIO_GPIO_OE_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OE_CLR_OFFSET: u32 = 40;
pub const SIO_GPIO_OE_CLR_BITS: u32 = 1073741823;
pub const SIO_GPIO_OE_CLR_RESET: u32 = 0;
pub const SIO_GPIO_OE_CLR_MSB: u32 = 29;
pub const SIO_GPIO_OE_CLR_LSB: u32 = 0;
pub const SIO_GPIO_OE_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_OE_XOR_OFFSET: u32 = 44;
pub const SIO_GPIO_OE_XOR_BITS: u32 = 1073741823;
pub const SIO_GPIO_OE_XOR_RESET: u32 = 0;
pub const SIO_GPIO_OE_XOR_MSB: u32 = 29;
pub const SIO_GPIO_OE_XOR_LSB: u32 = 0;
pub const SIO_GPIO_OE_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OUT_OFFSET: u32 = 48;
pub const SIO_GPIO_HI_OUT_BITS: u32 = 63;
pub const SIO_GPIO_HI_OUT_RESET: u32 = 0;
pub const SIO_GPIO_HI_OUT_MSB: u32 = 5;
pub const SIO_GPIO_HI_OUT_LSB: u32 = 0;
pub const SIO_GPIO_HI_OUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OUT_SET_OFFSET: u32 = 52;
pub const SIO_GPIO_HI_OUT_SET_BITS: u32 = 63;
pub const SIO_GPIO_HI_OUT_SET_RESET: u32 = 0;
pub const SIO_GPIO_HI_OUT_SET_MSB: u32 = 5;
pub const SIO_GPIO_HI_OUT_SET_LSB: u32 = 0;
pub const SIO_GPIO_HI_OUT_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OUT_CLR_OFFSET: u32 = 56;
pub const SIO_GPIO_HI_OUT_CLR_BITS: u32 = 63;
pub const SIO_GPIO_HI_OUT_CLR_RESET: u32 = 0;
pub const SIO_GPIO_HI_OUT_CLR_MSB: u32 = 5;
pub const SIO_GPIO_HI_OUT_CLR_LSB: u32 = 0;
pub const SIO_GPIO_HI_OUT_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OUT_XOR_OFFSET: u32 = 60;
pub const SIO_GPIO_HI_OUT_XOR_BITS: u32 = 63;
pub const SIO_GPIO_HI_OUT_XOR_RESET: u32 = 0;
pub const SIO_GPIO_HI_OUT_XOR_MSB: u32 = 5;
pub const SIO_GPIO_HI_OUT_XOR_LSB: u32 = 0;
pub const SIO_GPIO_HI_OUT_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OE_OFFSET: u32 = 64;
pub const SIO_GPIO_HI_OE_BITS: u32 = 63;
pub const SIO_GPIO_HI_OE_RESET: u32 = 0;
pub const SIO_GPIO_HI_OE_MSB: u32 = 5;
pub const SIO_GPIO_HI_OE_LSB: u32 = 0;
pub const SIO_GPIO_HI_OE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OE_SET_OFFSET: u32 = 68;
pub const SIO_GPIO_HI_OE_SET_BITS: u32 = 63;
pub const SIO_GPIO_HI_OE_SET_RESET: u32 = 0;
pub const SIO_GPIO_HI_OE_SET_MSB: u32 = 5;
pub const SIO_GPIO_HI_OE_SET_LSB: u32 = 0;
pub const SIO_GPIO_HI_OE_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OE_CLR_OFFSET: u32 = 72;
pub const SIO_GPIO_HI_OE_CLR_BITS: u32 = 63;
pub const SIO_GPIO_HI_OE_CLR_RESET: u32 = 0;
pub const SIO_GPIO_HI_OE_CLR_MSB: u32 = 5;
pub const SIO_GPIO_HI_OE_CLR_LSB: u32 = 0;
pub const SIO_GPIO_HI_OE_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_GPIO_HI_OE_XOR_OFFSET: u32 = 76;
pub const SIO_GPIO_HI_OE_XOR_BITS: u32 = 63;
pub const SIO_GPIO_HI_OE_XOR_RESET: u32 = 0;
pub const SIO_GPIO_HI_OE_XOR_MSB: u32 = 5;
pub const SIO_GPIO_HI_OE_XOR_LSB: u32 = 0;
pub const SIO_GPIO_HI_OE_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_FIFO_ST_OFFSET: u32 = 80;
pub const SIO_FIFO_ST_BITS: u32 = 15;
pub const SIO_FIFO_ST_RESET: u32 = 2;
pub const SIO_FIFO_ST_ROE_RESET: u32 = 0;
pub const SIO_FIFO_ST_ROE_BITS: u32 = 8;
pub const SIO_FIFO_ST_ROE_MSB: u32 = 3;
pub const SIO_FIFO_ST_ROE_LSB: u32 = 3;
pub const SIO_FIFO_ST_ROE_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const SIO_FIFO_ST_WOF_RESET: u32 = 0;
pub const SIO_FIFO_ST_WOF_BITS: u32 = 4;
pub const SIO_FIFO_ST_WOF_MSB: u32 = 2;
pub const SIO_FIFO_ST_WOF_LSB: u32 = 2;
pub const SIO_FIFO_ST_WOF_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const SIO_FIFO_ST_RDY_RESET: u32 = 1;
pub const SIO_FIFO_ST_RDY_BITS: u32 = 2;
pub const SIO_FIFO_ST_RDY_MSB: u32 = 1;
pub const SIO_FIFO_ST_RDY_LSB: u32 = 1;
pub const SIO_FIFO_ST_RDY_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_FIFO_ST_VLD_RESET: u32 = 0;
pub const SIO_FIFO_ST_VLD_BITS: u32 = 1;
pub const SIO_FIFO_ST_VLD_MSB: u32 = 0;
pub const SIO_FIFO_ST_VLD_LSB: u32 = 0;
pub const SIO_FIFO_ST_VLD_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_FIFO_WR_OFFSET: u32 = 84;
pub const SIO_FIFO_WR_BITS: u32 = 4294967295;
pub const SIO_FIFO_WR_RESET: u32 = 0;
pub const SIO_FIFO_WR_MSB: u32 = 31;
pub const SIO_FIFO_WR_LSB: u32 = 0;
pub const SIO_FIFO_WR_ACCESS: &'static [u8; 3usize] = b"WF\0";
pub const SIO_FIFO_RD_OFFSET: u32 = 88;
pub const SIO_FIFO_RD_BITS: u32 = 4294967295;
pub const SIO_FIFO_RD_RESET: &'static [u8; 2usize] = b"-\0";
pub const SIO_FIFO_RD_MSB: u32 = 31;
pub const SIO_FIFO_RD_LSB: u32 = 0;
pub const SIO_FIFO_RD_ACCESS: &'static [u8; 3usize] = b"RF\0";
pub const SIO_SPINLOCK_ST_OFFSET: u32 = 92;
pub const SIO_SPINLOCK_ST_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK_ST_RESET: u32 = 0;
pub const SIO_SPINLOCK_ST_MSB: u32 = 31;
pub const SIO_SPINLOCK_ST_LSB: u32 = 0;
pub const SIO_SPINLOCK_ST_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_DIV_UDIVIDEND_OFFSET: u32 = 96;
pub const SIO_DIV_UDIVIDEND_BITS: u32 = 4294967295;
pub const SIO_DIV_UDIVIDEND_RESET: u32 = 0;
pub const SIO_DIV_UDIVIDEND_MSB: u32 = 31;
pub const SIO_DIV_UDIVIDEND_LSB: u32 = 0;
pub const SIO_DIV_UDIVIDEND_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_DIV_UDIVISOR_OFFSET: u32 = 100;
pub const SIO_DIV_UDIVISOR_BITS: u32 = 4294967295;
pub const SIO_DIV_UDIVISOR_RESET: u32 = 0;
pub const SIO_DIV_UDIVISOR_MSB: u32 = 31;
pub const SIO_DIV_UDIVISOR_LSB: u32 = 0;
pub const SIO_DIV_UDIVISOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_DIV_SDIVIDEND_OFFSET: u32 = 104;
pub const SIO_DIV_SDIVIDEND_BITS: u32 = 4294967295;
pub const SIO_DIV_SDIVIDEND_RESET: u32 = 0;
pub const SIO_DIV_SDIVIDEND_MSB: u32 = 31;
pub const SIO_DIV_SDIVIDEND_LSB: u32 = 0;
pub const SIO_DIV_SDIVIDEND_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_DIV_SDIVISOR_OFFSET: u32 = 108;
pub const SIO_DIV_SDIVISOR_BITS: u32 = 4294967295;
pub const SIO_DIV_SDIVISOR_RESET: u32 = 0;
pub const SIO_DIV_SDIVISOR_MSB: u32 = 31;
pub const SIO_DIV_SDIVISOR_LSB: u32 = 0;
pub const SIO_DIV_SDIVISOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_DIV_QUOTIENT_OFFSET: u32 = 112;
pub const SIO_DIV_QUOTIENT_BITS: u32 = 4294967295;
pub const SIO_DIV_QUOTIENT_RESET: u32 = 0;
pub const SIO_DIV_QUOTIENT_MSB: u32 = 31;
pub const SIO_DIV_QUOTIENT_LSB: u32 = 0;
pub const SIO_DIV_QUOTIENT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_DIV_REMAINDER_OFFSET: u32 = 116;
pub const SIO_DIV_REMAINDER_BITS: u32 = 4294967295;
pub const SIO_DIV_REMAINDER_RESET: u32 = 0;
pub const SIO_DIV_REMAINDER_MSB: u32 = 31;
pub const SIO_DIV_REMAINDER_LSB: u32 = 0;
pub const SIO_DIV_REMAINDER_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_DIV_CSR_OFFSET: u32 = 120;
pub const SIO_DIV_CSR_BITS: u32 = 3;
pub const SIO_DIV_CSR_RESET: u32 = 1;
pub const SIO_DIV_CSR_DIRTY_RESET: u32 = 0;
pub const SIO_DIV_CSR_DIRTY_BITS: u32 = 2;
pub const SIO_DIV_CSR_DIRTY_MSB: u32 = 1;
pub const SIO_DIV_CSR_DIRTY_LSB: u32 = 1;
pub const SIO_DIV_CSR_DIRTY_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_DIV_CSR_READY_RESET: u32 = 1;
pub const SIO_DIV_CSR_READY_BITS: u32 = 1;
pub const SIO_DIV_CSR_READY_MSB: u32 = 0;
pub const SIO_DIV_CSR_READY_LSB: u32 = 0;
pub const SIO_DIV_CSR_READY_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_ACCUM0_OFFSET: u32 = 128;
pub const SIO_INTERP0_ACCUM0_BITS: u32 = 4294967295;
pub const SIO_INTERP0_ACCUM0_RESET: u32 = 0;
pub const SIO_INTERP0_ACCUM0_MSB: u32 = 31;
pub const SIO_INTERP0_ACCUM0_LSB: u32 = 0;
pub const SIO_INTERP0_ACCUM0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_ACCUM1_OFFSET: u32 = 132;
pub const SIO_INTERP0_ACCUM1_BITS: u32 = 4294967295;
pub const SIO_INTERP0_ACCUM1_RESET: u32 = 0;
pub const SIO_INTERP0_ACCUM1_MSB: u32 = 31;
pub const SIO_INTERP0_ACCUM1_LSB: u32 = 0;
pub const SIO_INTERP0_ACCUM1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_BASE0_OFFSET: u32 = 136;
pub const SIO_INTERP0_BASE0_BITS: u32 = 4294967295;
pub const SIO_INTERP0_BASE0_RESET: u32 = 0;
pub const SIO_INTERP0_BASE0_MSB: u32 = 31;
pub const SIO_INTERP0_BASE0_LSB: u32 = 0;
pub const SIO_INTERP0_BASE0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_BASE1_OFFSET: u32 = 140;
pub const SIO_INTERP0_BASE1_BITS: u32 = 4294967295;
pub const SIO_INTERP0_BASE1_RESET: u32 = 0;
pub const SIO_INTERP0_BASE1_MSB: u32 = 31;
pub const SIO_INTERP0_BASE1_LSB: u32 = 0;
pub const SIO_INTERP0_BASE1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_BASE2_OFFSET: u32 = 144;
pub const SIO_INTERP0_BASE2_BITS: u32 = 4294967295;
pub const SIO_INTERP0_BASE2_RESET: u32 = 0;
pub const SIO_INTERP0_BASE2_MSB: u32 = 31;
pub const SIO_INTERP0_BASE2_LSB: u32 = 0;
pub const SIO_INTERP0_BASE2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_POP_LANE0_OFFSET: u32 = 148;
pub const SIO_INTERP0_POP_LANE0_BITS: u32 = 4294967295;
pub const SIO_INTERP0_POP_LANE0_RESET: u32 = 0;
pub const SIO_INTERP0_POP_LANE0_MSB: u32 = 31;
pub const SIO_INTERP0_POP_LANE0_LSB: u32 = 0;
pub const SIO_INTERP0_POP_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_POP_LANE1_OFFSET: u32 = 152;
pub const SIO_INTERP0_POP_LANE1_BITS: u32 = 4294967295;
pub const SIO_INTERP0_POP_LANE1_RESET: u32 = 0;
pub const SIO_INTERP0_POP_LANE1_MSB: u32 = 31;
pub const SIO_INTERP0_POP_LANE1_LSB: u32 = 0;
pub const SIO_INTERP0_POP_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_POP_FULL_OFFSET: u32 = 156;
pub const SIO_INTERP0_POP_FULL_BITS: u32 = 4294967295;
pub const SIO_INTERP0_POP_FULL_RESET: u32 = 0;
pub const SIO_INTERP0_POP_FULL_MSB: u32 = 31;
pub const SIO_INTERP0_POP_FULL_LSB: u32 = 0;
pub const SIO_INTERP0_POP_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_PEEK_LANE0_OFFSET: u32 = 160;
pub const SIO_INTERP0_PEEK_LANE0_BITS: u32 = 4294967295;
pub const SIO_INTERP0_PEEK_LANE0_RESET: u32 = 0;
pub const SIO_INTERP0_PEEK_LANE0_MSB: u32 = 31;
pub const SIO_INTERP0_PEEK_LANE0_LSB: u32 = 0;
pub const SIO_INTERP0_PEEK_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_PEEK_LANE1_OFFSET: u32 = 164;
pub const SIO_INTERP0_PEEK_LANE1_BITS: u32 = 4294967295;
pub const SIO_INTERP0_PEEK_LANE1_RESET: u32 = 0;
pub const SIO_INTERP0_PEEK_LANE1_MSB: u32 = 31;
pub const SIO_INTERP0_PEEK_LANE1_LSB: u32 = 0;
pub const SIO_INTERP0_PEEK_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_PEEK_FULL_OFFSET: u32 = 168;
pub const SIO_INTERP0_PEEK_FULL_BITS: u32 = 4294967295;
pub const SIO_INTERP0_PEEK_FULL_RESET: u32 = 0;
pub const SIO_INTERP0_PEEK_FULL_MSB: u32 = 31;
pub const SIO_INTERP0_PEEK_FULL_LSB: u32 = 0;
pub const SIO_INTERP0_PEEK_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_CTRL_LANE0_OFFSET: u32 = 172;
pub const SIO_INTERP0_CTRL_LANE0_BITS: u32 = 62914559;
pub const SIO_INTERP0_CTRL_LANE0_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_OVERF_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_OVERF_BITS: u32 = 33554432;
pub const SIO_INTERP0_CTRL_LANE0_OVERF_MSB: u32 = 25;
pub const SIO_INTERP0_CTRL_LANE0_OVERF_LSB: u32 = 25;
pub const SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_CTRL_LANE0_OVERF1_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_OVERF1_BITS: u32 = 16777216;
pub const SIO_INTERP0_CTRL_LANE0_OVERF1_MSB: u32 = 24;
pub const SIO_INTERP0_CTRL_LANE0_OVERF1_LSB: u32 = 24;
pub const SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_CTRL_LANE0_OVERF0_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_OVERF0_BITS: u32 = 8388608;
pub const SIO_INTERP0_CTRL_LANE0_OVERF0_MSB: u32 = 23;
pub const SIO_INTERP0_CTRL_LANE0_OVERF0_LSB: u32 = 23;
pub const SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP0_CTRL_LANE0_BLEND_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_BLEND_BITS: u32 = 2097152;
pub const SIO_INTERP0_CTRL_LANE0_BLEND_MSB: u32 = 21;
pub const SIO_INTERP0_CTRL_LANE0_BLEND_LSB: u32 = 21;
pub const SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS: u32 = 1572864;
pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB: u32 = 20;
pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB: u32 = 19;
pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS: u32 = 262144;
pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB: u32 = 18;
pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB: u32 = 18;
pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS: u32 = 131072;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB: u32 = 17;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB: u32 = 17;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS: u32 = 65536;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB: u32 = 16;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB: u32 = 16;
pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_SIGNED_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_SIGNED_BITS: u32 = 32768;
pub const SIO_INTERP0_CTRL_LANE0_SIGNED_MSB: u32 = 15;
pub const SIO_INTERP0_CTRL_LANE0_SIGNED_LSB: u32 = 15;
pub const SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS: u32 = 31744;
pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB: u32 = 14;
pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB: u32 = 10;
pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS: u32 = 992;
pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB: u32 = 9;
pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB: u32 = 5;
pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE0_SHIFT_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_SHIFT_BITS: u32 = 31;
pub const SIO_INTERP0_CTRL_LANE0_SHIFT_MSB: u32 = 4;
pub const SIO_INTERP0_CTRL_LANE0_SHIFT_LSB: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_OFFSET: u32 = 176;
pub const SIO_INTERP0_CTRL_LANE1_BITS: u32 = 2097151;
pub const SIO_INTERP0_CTRL_LANE1_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS: u32 = 1572864;
pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB: u32 = 20;
pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB: u32 = 19;
pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS: u32 = 262144;
pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB: u32 = 18;
pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB: u32 = 18;
pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS: u32 = 131072;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB: u32 = 17;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB: u32 = 17;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS: u32 = 65536;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB: u32 = 16;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB: u32 = 16;
pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_SIGNED_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_SIGNED_BITS: u32 = 32768;
pub const SIO_INTERP0_CTRL_LANE1_SIGNED_MSB: u32 = 15;
pub const SIO_INTERP0_CTRL_LANE1_SIGNED_LSB: u32 = 15;
pub const SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS: u32 = 31744;
pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB: u32 = 14;
pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB: u32 = 10;
pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS: u32 = 992;
pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB: u32 = 9;
pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB: u32 = 5;
pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_CTRL_LANE1_SHIFT_RESET: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_SHIFT_BITS: u32 = 31;
pub const SIO_INTERP0_CTRL_LANE1_SHIFT_MSB: u32 = 4;
pub const SIO_INTERP0_CTRL_LANE1_SHIFT_LSB: u32 = 0;
pub const SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_ACCUM0_ADD_OFFSET: u32 = 180;
pub const SIO_INTERP0_ACCUM0_ADD_BITS: u32 = 16777215;
pub const SIO_INTERP0_ACCUM0_ADD_RESET: u32 = 0;
pub const SIO_INTERP0_ACCUM0_ADD_MSB: u32 = 23;
pub const SIO_INTERP0_ACCUM0_ADD_LSB: u32 = 0;
pub const SIO_INTERP0_ACCUM0_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_ACCUM1_ADD_OFFSET: u32 = 184;
pub const SIO_INTERP0_ACCUM1_ADD_BITS: u32 = 16777215;
pub const SIO_INTERP0_ACCUM1_ADD_RESET: u32 = 0;
pub const SIO_INTERP0_ACCUM1_ADD_MSB: u32 = 23;
pub const SIO_INTERP0_ACCUM1_ADD_LSB: u32 = 0;
pub const SIO_INTERP0_ACCUM1_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP0_BASE_1AND0_OFFSET: u32 = 188;
pub const SIO_INTERP0_BASE_1AND0_BITS: u32 = 4294967295;
pub const SIO_INTERP0_BASE_1AND0_RESET: u32 = 0;
pub const SIO_INTERP0_BASE_1AND0_MSB: u32 = 31;
pub const SIO_INTERP0_BASE_1AND0_LSB: u32 = 0;
pub const SIO_INTERP0_BASE_1AND0_ACCESS: &'static [u8; 3usize] = b"WO\0";
pub const SIO_INTERP1_ACCUM0_OFFSET: u32 = 192;
pub const SIO_INTERP1_ACCUM0_BITS: u32 = 4294967295;
pub const SIO_INTERP1_ACCUM0_RESET: u32 = 0;
pub const SIO_INTERP1_ACCUM0_MSB: u32 = 31;
pub const SIO_INTERP1_ACCUM0_LSB: u32 = 0;
pub const SIO_INTERP1_ACCUM0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_ACCUM1_OFFSET: u32 = 196;
pub const SIO_INTERP1_ACCUM1_BITS: u32 = 4294967295;
pub const SIO_INTERP1_ACCUM1_RESET: u32 = 0;
pub const SIO_INTERP1_ACCUM1_MSB: u32 = 31;
pub const SIO_INTERP1_ACCUM1_LSB: u32 = 0;
pub const SIO_INTERP1_ACCUM1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_BASE0_OFFSET: u32 = 200;
pub const SIO_INTERP1_BASE0_BITS: u32 = 4294967295;
pub const SIO_INTERP1_BASE0_RESET: u32 = 0;
pub const SIO_INTERP1_BASE0_MSB: u32 = 31;
pub const SIO_INTERP1_BASE0_LSB: u32 = 0;
pub const SIO_INTERP1_BASE0_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_BASE1_OFFSET: u32 = 204;
pub const SIO_INTERP1_BASE1_BITS: u32 = 4294967295;
pub const SIO_INTERP1_BASE1_RESET: u32 = 0;
pub const SIO_INTERP1_BASE1_MSB: u32 = 31;
pub const SIO_INTERP1_BASE1_LSB: u32 = 0;
pub const SIO_INTERP1_BASE1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_BASE2_OFFSET: u32 = 208;
pub const SIO_INTERP1_BASE2_BITS: u32 = 4294967295;
pub const SIO_INTERP1_BASE2_RESET: u32 = 0;
pub const SIO_INTERP1_BASE2_MSB: u32 = 31;
pub const SIO_INTERP1_BASE2_LSB: u32 = 0;
pub const SIO_INTERP1_BASE2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_POP_LANE0_OFFSET: u32 = 212;
pub const SIO_INTERP1_POP_LANE0_BITS: u32 = 4294967295;
pub const SIO_INTERP1_POP_LANE0_RESET: u32 = 0;
pub const SIO_INTERP1_POP_LANE0_MSB: u32 = 31;
pub const SIO_INTERP1_POP_LANE0_LSB: u32 = 0;
pub const SIO_INTERP1_POP_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_POP_LANE1_OFFSET: u32 = 216;
pub const SIO_INTERP1_POP_LANE1_BITS: u32 = 4294967295;
pub const SIO_INTERP1_POP_LANE1_RESET: u32 = 0;
pub const SIO_INTERP1_POP_LANE1_MSB: u32 = 31;
pub const SIO_INTERP1_POP_LANE1_LSB: u32 = 0;
pub const SIO_INTERP1_POP_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_POP_FULL_OFFSET: u32 = 220;
pub const SIO_INTERP1_POP_FULL_BITS: u32 = 4294967295;
pub const SIO_INTERP1_POP_FULL_RESET: u32 = 0;
pub const SIO_INTERP1_POP_FULL_MSB: u32 = 31;
pub const SIO_INTERP1_POP_FULL_LSB: u32 = 0;
pub const SIO_INTERP1_POP_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_PEEK_LANE0_OFFSET: u32 = 224;
pub const SIO_INTERP1_PEEK_LANE0_BITS: u32 = 4294967295;
pub const SIO_INTERP1_PEEK_LANE0_RESET: u32 = 0;
pub const SIO_INTERP1_PEEK_LANE0_MSB: u32 = 31;
pub const SIO_INTERP1_PEEK_LANE0_LSB: u32 = 0;
pub const SIO_INTERP1_PEEK_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_PEEK_LANE1_OFFSET: u32 = 228;
pub const SIO_INTERP1_PEEK_LANE1_BITS: u32 = 4294967295;
pub const SIO_INTERP1_PEEK_LANE1_RESET: u32 = 0;
pub const SIO_INTERP1_PEEK_LANE1_MSB: u32 = 31;
pub const SIO_INTERP1_PEEK_LANE1_LSB: u32 = 0;
pub const SIO_INTERP1_PEEK_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_PEEK_FULL_OFFSET: u32 = 232;
pub const SIO_INTERP1_PEEK_FULL_BITS: u32 = 4294967295;
pub const SIO_INTERP1_PEEK_FULL_RESET: u32 = 0;
pub const SIO_INTERP1_PEEK_FULL_MSB: u32 = 31;
pub const SIO_INTERP1_PEEK_FULL_LSB: u32 = 0;
pub const SIO_INTERP1_PEEK_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_CTRL_LANE0_OFFSET: u32 = 236;
pub const SIO_INTERP1_CTRL_LANE0_BITS: u32 = 65011711;
pub const SIO_INTERP1_CTRL_LANE0_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_OVERF_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_OVERF_BITS: u32 = 33554432;
pub const SIO_INTERP1_CTRL_LANE0_OVERF_MSB: u32 = 25;
pub const SIO_INTERP1_CTRL_LANE0_OVERF_LSB: u32 = 25;
pub const SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_CTRL_LANE0_OVERF1_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_OVERF1_BITS: u32 = 16777216;
pub const SIO_INTERP1_CTRL_LANE0_OVERF1_MSB: u32 = 24;
pub const SIO_INTERP1_CTRL_LANE0_OVERF1_LSB: u32 = 24;
pub const SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_CTRL_LANE0_OVERF0_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_OVERF0_BITS: u32 = 8388608;
pub const SIO_INTERP1_CTRL_LANE0_OVERF0_MSB: u32 = 23;
pub const SIO_INTERP1_CTRL_LANE0_OVERF0_LSB: u32 = 23;
pub const SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_INTERP1_CTRL_LANE0_CLAMP_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_CLAMP_BITS: u32 = 4194304;
pub const SIO_INTERP1_CTRL_LANE0_CLAMP_MSB: u32 = 22;
pub const SIO_INTERP1_CTRL_LANE0_CLAMP_LSB: u32 = 22;
pub const SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS: u32 = 1572864;
pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB: u32 = 20;
pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB: u32 = 19;
pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS: u32 = 262144;
pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB: u32 = 18;
pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB: u32 = 18;
pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS: u32 = 131072;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB: u32 = 17;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB: u32 = 17;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS: u32 = 65536;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB: u32 = 16;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB: u32 = 16;
pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_SIGNED_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_SIGNED_BITS: u32 = 32768;
pub const SIO_INTERP1_CTRL_LANE0_SIGNED_MSB: u32 = 15;
pub const SIO_INTERP1_CTRL_LANE0_SIGNED_LSB: u32 = 15;
pub const SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS: u32 = 31744;
pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB: u32 = 14;
pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB: u32 = 10;
pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS: u32 = 992;
pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB: u32 = 9;
pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB: u32 = 5;
pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE0_SHIFT_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_SHIFT_BITS: u32 = 31;
pub const SIO_INTERP1_CTRL_LANE0_SHIFT_MSB: u32 = 4;
pub const SIO_INTERP1_CTRL_LANE0_SHIFT_LSB: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_OFFSET: u32 = 240;
pub const SIO_INTERP1_CTRL_LANE1_BITS: u32 = 2097151;
pub const SIO_INTERP1_CTRL_LANE1_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS: u32 = 1572864;
pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB: u32 = 20;
pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB: u32 = 19;
pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS: u32 = 262144;
pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB: u32 = 18;
pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB: u32 = 18;
pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS: u32 = 131072;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB: u32 = 17;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB: u32 = 17;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS: u32 = 65536;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB: u32 = 16;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB: u32 = 16;
pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_SIGNED_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_SIGNED_BITS: u32 = 32768;
pub const SIO_INTERP1_CTRL_LANE1_SIGNED_MSB: u32 = 15;
pub const SIO_INTERP1_CTRL_LANE1_SIGNED_LSB: u32 = 15;
pub const SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS: u32 = 31744;
pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB: u32 = 14;
pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB: u32 = 10;
pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS: u32 = 992;
pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB: u32 = 9;
pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB: u32 = 5;
pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_CTRL_LANE1_SHIFT_RESET: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_SHIFT_BITS: u32 = 31;
pub const SIO_INTERP1_CTRL_LANE1_SHIFT_MSB: u32 = 4;
pub const SIO_INTERP1_CTRL_LANE1_SHIFT_LSB: u32 = 0;
pub const SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_ACCUM0_ADD_OFFSET: u32 = 244;
pub const SIO_INTERP1_ACCUM0_ADD_BITS: u32 = 16777215;
pub const SIO_INTERP1_ACCUM0_ADD_RESET: u32 = 0;
pub const SIO_INTERP1_ACCUM0_ADD_MSB: u32 = 23;
pub const SIO_INTERP1_ACCUM0_ADD_LSB: u32 = 0;
pub const SIO_INTERP1_ACCUM0_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_ACCUM1_ADD_OFFSET: u32 = 248;
pub const SIO_INTERP1_ACCUM1_ADD_BITS: u32 = 16777215;
pub const SIO_INTERP1_ACCUM1_ADD_RESET: u32 = 0;
pub const SIO_INTERP1_ACCUM1_ADD_MSB: u32 = 23;
pub const SIO_INTERP1_ACCUM1_ADD_LSB: u32 = 0;
pub const SIO_INTERP1_ACCUM1_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const SIO_INTERP1_BASE_1AND0_OFFSET: u32 = 252;
pub const SIO_INTERP1_BASE_1AND0_BITS: u32 = 4294967295;
pub const SIO_INTERP1_BASE_1AND0_RESET: u32 = 0;
pub const SIO_INTERP1_BASE_1AND0_MSB: u32 = 31;
pub const SIO_INTERP1_BASE_1AND0_LSB: u32 = 0;
pub const SIO_INTERP1_BASE_1AND0_ACCESS: &'static [u8; 3usize] = b"WO\0";
pub const SIO_SPINLOCK0_OFFSET: u32 = 256;
pub const SIO_SPINLOCK0_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK0_RESET: u32 = 0;
pub const SIO_SPINLOCK0_MSB: u32 = 31;
pub const SIO_SPINLOCK0_LSB: u32 = 0;
pub const SIO_SPINLOCK0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK1_OFFSET: u32 = 260;
pub const SIO_SPINLOCK1_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK1_RESET: u32 = 0;
pub const SIO_SPINLOCK1_MSB: u32 = 31;
pub const SIO_SPINLOCK1_LSB: u32 = 0;
pub const SIO_SPINLOCK1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK2_OFFSET: u32 = 264;
pub const SIO_SPINLOCK2_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK2_RESET: u32 = 0;
pub const SIO_SPINLOCK2_MSB: u32 = 31;
pub const SIO_SPINLOCK2_LSB: u32 = 0;
pub const SIO_SPINLOCK2_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK3_OFFSET: u32 = 268;
pub const SIO_SPINLOCK3_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK3_RESET: u32 = 0;
pub const SIO_SPINLOCK3_MSB: u32 = 31;
pub const SIO_SPINLOCK3_LSB: u32 = 0;
pub const SIO_SPINLOCK3_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK4_OFFSET: u32 = 272;
pub const SIO_SPINLOCK4_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK4_RESET: u32 = 0;
pub const SIO_SPINLOCK4_MSB: u32 = 31;
pub const SIO_SPINLOCK4_LSB: u32 = 0;
pub const SIO_SPINLOCK4_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK5_OFFSET: u32 = 276;
pub const SIO_SPINLOCK5_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK5_RESET: u32 = 0;
pub const SIO_SPINLOCK5_MSB: u32 = 31;
pub const SIO_SPINLOCK5_LSB: u32 = 0;
pub const SIO_SPINLOCK5_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK6_OFFSET: u32 = 280;
pub const SIO_SPINLOCK6_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK6_RESET: u32 = 0;
pub const SIO_SPINLOCK6_MSB: u32 = 31;
pub const SIO_SPINLOCK6_LSB: u32 = 0;
pub const SIO_SPINLOCK6_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK7_OFFSET: u32 = 284;
pub const SIO_SPINLOCK7_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK7_RESET: u32 = 0;
pub const SIO_SPINLOCK7_MSB: u32 = 31;
pub const SIO_SPINLOCK7_LSB: u32 = 0;
pub const SIO_SPINLOCK7_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK8_OFFSET: u32 = 288;
pub const SIO_SPINLOCK8_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK8_RESET: u32 = 0;
pub const SIO_SPINLOCK8_MSB: u32 = 31;
pub const SIO_SPINLOCK8_LSB: u32 = 0;
pub const SIO_SPINLOCK8_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK9_OFFSET: u32 = 292;
pub const SIO_SPINLOCK9_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK9_RESET: u32 = 0;
pub const SIO_SPINLOCK9_MSB: u32 = 31;
pub const SIO_SPINLOCK9_LSB: u32 = 0;
pub const SIO_SPINLOCK9_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK10_OFFSET: u32 = 296;
pub const SIO_SPINLOCK10_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK10_RESET: u32 = 0;
pub const SIO_SPINLOCK10_MSB: u32 = 31;
pub const SIO_SPINLOCK10_LSB: u32 = 0;
pub const SIO_SPINLOCK10_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK11_OFFSET: u32 = 300;
pub const SIO_SPINLOCK11_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK11_RESET: u32 = 0;
pub const SIO_SPINLOCK11_MSB: u32 = 31;
pub const SIO_SPINLOCK11_LSB: u32 = 0;
pub const SIO_SPINLOCK11_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK12_OFFSET: u32 = 304;
pub const SIO_SPINLOCK12_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK12_RESET: u32 = 0;
pub const SIO_SPINLOCK12_MSB: u32 = 31;
pub const SIO_SPINLOCK12_LSB: u32 = 0;
pub const SIO_SPINLOCK12_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK13_OFFSET: u32 = 308;
pub const SIO_SPINLOCK13_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK13_RESET: u32 = 0;
pub const SIO_SPINLOCK13_MSB: u32 = 31;
pub const SIO_SPINLOCK13_LSB: u32 = 0;
pub const SIO_SPINLOCK13_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK14_OFFSET: u32 = 312;
pub const SIO_SPINLOCK14_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK14_RESET: u32 = 0;
pub const SIO_SPINLOCK14_MSB: u32 = 31;
pub const SIO_SPINLOCK14_LSB: u32 = 0;
pub const SIO_SPINLOCK14_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK15_OFFSET: u32 = 316;
pub const SIO_SPINLOCK15_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK15_RESET: u32 = 0;
pub const SIO_SPINLOCK15_MSB: u32 = 31;
pub const SIO_SPINLOCK15_LSB: u32 = 0;
pub const SIO_SPINLOCK15_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK16_OFFSET: u32 = 320;
pub const SIO_SPINLOCK16_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK16_RESET: u32 = 0;
pub const SIO_SPINLOCK16_MSB: u32 = 31;
pub const SIO_SPINLOCK16_LSB: u32 = 0;
pub const SIO_SPINLOCK16_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK17_OFFSET: u32 = 324;
pub const SIO_SPINLOCK17_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK17_RESET: u32 = 0;
pub const SIO_SPINLOCK17_MSB: u32 = 31;
pub const SIO_SPINLOCK17_LSB: u32 = 0;
pub const SIO_SPINLOCK17_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK18_OFFSET: u32 = 328;
pub const SIO_SPINLOCK18_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK18_RESET: u32 = 0;
pub const SIO_SPINLOCK18_MSB: u32 = 31;
pub const SIO_SPINLOCK18_LSB: u32 = 0;
pub const SIO_SPINLOCK18_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK19_OFFSET: u32 = 332;
pub const SIO_SPINLOCK19_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK19_RESET: u32 = 0;
pub const SIO_SPINLOCK19_MSB: u32 = 31;
pub const SIO_SPINLOCK19_LSB: u32 = 0;
pub const SIO_SPINLOCK19_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK20_OFFSET: u32 = 336;
pub const SIO_SPINLOCK20_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK20_RESET: u32 = 0;
pub const SIO_SPINLOCK20_MSB: u32 = 31;
pub const SIO_SPINLOCK20_LSB: u32 = 0;
pub const SIO_SPINLOCK20_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK21_OFFSET: u32 = 340;
pub const SIO_SPINLOCK21_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK21_RESET: u32 = 0;
pub const SIO_SPINLOCK21_MSB: u32 = 31;
pub const SIO_SPINLOCK21_LSB: u32 = 0;
pub const SIO_SPINLOCK21_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK22_OFFSET: u32 = 344;
pub const SIO_SPINLOCK22_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK22_RESET: u32 = 0;
pub const SIO_SPINLOCK22_MSB: u32 = 31;
pub const SIO_SPINLOCK22_LSB: u32 = 0;
pub const SIO_SPINLOCK22_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK23_OFFSET: u32 = 348;
pub const SIO_SPINLOCK23_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK23_RESET: u32 = 0;
pub const SIO_SPINLOCK23_MSB: u32 = 31;
pub const SIO_SPINLOCK23_LSB: u32 = 0;
pub const SIO_SPINLOCK23_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK24_OFFSET: u32 = 352;
pub const SIO_SPINLOCK24_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK24_RESET: u32 = 0;
pub const SIO_SPINLOCK24_MSB: u32 = 31;
pub const SIO_SPINLOCK24_LSB: u32 = 0;
pub const SIO_SPINLOCK24_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK25_OFFSET: u32 = 356;
pub const SIO_SPINLOCK25_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK25_RESET: u32 = 0;
pub const SIO_SPINLOCK25_MSB: u32 = 31;
pub const SIO_SPINLOCK25_LSB: u32 = 0;
pub const SIO_SPINLOCK25_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK26_OFFSET: u32 = 360;
pub const SIO_SPINLOCK26_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK26_RESET: u32 = 0;
pub const SIO_SPINLOCK26_MSB: u32 = 31;
pub const SIO_SPINLOCK26_LSB: u32 = 0;
pub const SIO_SPINLOCK26_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK27_OFFSET: u32 = 364;
pub const SIO_SPINLOCK27_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK27_RESET: u32 = 0;
pub const SIO_SPINLOCK27_MSB: u32 = 31;
pub const SIO_SPINLOCK27_LSB: u32 = 0;
pub const SIO_SPINLOCK27_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK28_OFFSET: u32 = 368;
pub const SIO_SPINLOCK28_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK28_RESET: u32 = 0;
pub const SIO_SPINLOCK28_MSB: u32 = 31;
pub const SIO_SPINLOCK28_LSB: u32 = 0;
pub const SIO_SPINLOCK28_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK29_OFFSET: u32 = 372;
pub const SIO_SPINLOCK29_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK29_RESET: u32 = 0;
pub const SIO_SPINLOCK29_MSB: u32 = 31;
pub const SIO_SPINLOCK29_LSB: u32 = 0;
pub const SIO_SPINLOCK29_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK30_OFFSET: u32 = 376;
pub const SIO_SPINLOCK30_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK30_RESET: u32 = 0;
pub const SIO_SPINLOCK30_MSB: u32 = 31;
pub const SIO_SPINLOCK30_LSB: u32 = 0;
pub const SIO_SPINLOCK30_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const SIO_SPINLOCK31_OFFSET: u32 = 380;
pub const SIO_SPINLOCK31_BITS: u32 = 4294967295;
pub const SIO_SPINLOCK31_RESET: u32 = 0;
pub const SIO_SPINLOCK31_MSB: u32 = 31;
pub const SIO_SPINLOCK31_LSB: u32 = 0;
pub const SIO_SPINLOCK31_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const PADS_BANK0_VOLTAGE_SELECT_OFFSET: u32 = 0;
pub const PADS_BANK0_VOLTAGE_SELECT_BITS: u32 = 1;
pub const PADS_BANK0_VOLTAGE_SELECT_RESET: u32 = 0;
pub const PADS_BANK0_VOLTAGE_SELECT_MSB: u32 = 0;
pub const PADS_BANK0_VOLTAGE_SELECT_LSB: u32 = 0;
pub const PADS_BANK0_VOLTAGE_SELECT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3: u32 = 0;
pub const PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8: u32 = 1;
pub const PADS_BANK0_GPIO0_OFFSET: u32 = 4;
pub const PADS_BANK0_GPIO0_BITS: u32 = 255;
pub const PADS_BANK0_GPIO0_RESET: u32 = 86;
pub const PADS_BANK0_GPIO0_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO0_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO0_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO0_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO0_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO0_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO0_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO0_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO0_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO0_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO0_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO0_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO0_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO0_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO0_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO0_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO0_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO0_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO0_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO0_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO0_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO0_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO0_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO0_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO0_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO0_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO0_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO0_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO0_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO0_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO0_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO0_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO0_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO0_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO0_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO0_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO0_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO0_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO0_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_OFFSET: u32 = 8;
pub const PADS_BANK0_GPIO1_BITS: u32 = 255;
pub const PADS_BANK0_GPIO1_RESET: u32 = 86;
pub const PADS_BANK0_GPIO1_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO1_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO1_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO1_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO1_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO1_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO1_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO1_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO1_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO1_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO1_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO1_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO1_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO1_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO1_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO1_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO1_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO1_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO1_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO1_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO1_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO1_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO1_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO1_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO1_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO1_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO1_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO1_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO1_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO1_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO1_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO1_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO1_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO1_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_OFFSET: u32 = 12;
pub const PADS_BANK0_GPIO2_BITS: u32 = 255;
pub const PADS_BANK0_GPIO2_RESET: u32 = 86;
pub const PADS_BANK0_GPIO2_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO2_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO2_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO2_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO2_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO2_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO2_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO2_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO2_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO2_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO2_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO2_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO2_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO2_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO2_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO2_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO2_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO2_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO2_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO2_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO2_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO2_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO2_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO2_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO2_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO2_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO2_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO2_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO2_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO2_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO2_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO2_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO2_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO2_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_OFFSET: u32 = 16;
pub const PADS_BANK0_GPIO3_BITS: u32 = 255;
pub const PADS_BANK0_GPIO3_RESET: u32 = 86;
pub const PADS_BANK0_GPIO3_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO3_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO3_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO3_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO3_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO3_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO3_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO3_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO3_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO3_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO3_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO3_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO3_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO3_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO3_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO3_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO3_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO3_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO3_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO3_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO3_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO3_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO3_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO3_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO3_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO3_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO3_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO3_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO3_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO3_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO3_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO3_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO3_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO3_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_OFFSET: u32 = 20;
pub const PADS_BANK0_GPIO4_BITS: u32 = 255;
pub const PADS_BANK0_GPIO4_RESET: u32 = 86;
pub const PADS_BANK0_GPIO4_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO4_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO4_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO4_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO4_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO4_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO4_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO4_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO4_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO4_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO4_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO4_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO4_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO4_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO4_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO4_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO4_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO4_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO4_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO4_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO4_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO4_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO4_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO4_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO4_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO4_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO4_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO4_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO4_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO4_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO4_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO4_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO4_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO4_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_OFFSET: u32 = 24;
pub const PADS_BANK0_GPIO5_BITS: u32 = 255;
pub const PADS_BANK0_GPIO5_RESET: u32 = 86;
pub const PADS_BANK0_GPIO5_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO5_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO5_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO5_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO5_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO5_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO5_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO5_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO5_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO5_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO5_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO5_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO5_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO5_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO5_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO5_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO5_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO5_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO5_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO5_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO5_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO5_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO5_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO5_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO5_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO5_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO5_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO5_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO5_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO5_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO5_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO5_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO5_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO5_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_OFFSET: u32 = 28;
pub const PADS_BANK0_GPIO6_BITS: u32 = 255;
pub const PADS_BANK0_GPIO6_RESET: u32 = 86;
pub const PADS_BANK0_GPIO6_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO6_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO6_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO6_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO6_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO6_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO6_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO6_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO6_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO6_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO6_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO6_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO6_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO6_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO6_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO6_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO6_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO6_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO6_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO6_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO6_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO6_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO6_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO6_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO6_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO6_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO6_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO6_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO6_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO6_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO6_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO6_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO6_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO6_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_OFFSET: u32 = 32;
pub const PADS_BANK0_GPIO7_BITS: u32 = 255;
pub const PADS_BANK0_GPIO7_RESET: u32 = 86;
pub const PADS_BANK0_GPIO7_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO7_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO7_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO7_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO7_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO7_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO7_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO7_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO7_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO7_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO7_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO7_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO7_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO7_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO7_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO7_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO7_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO7_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO7_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO7_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO7_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO7_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO7_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO7_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO7_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO7_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO7_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO7_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO7_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO7_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO7_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO7_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO7_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO7_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_OFFSET: u32 = 36;
pub const PADS_BANK0_GPIO8_BITS: u32 = 255;
pub const PADS_BANK0_GPIO8_RESET: u32 = 86;
pub const PADS_BANK0_GPIO8_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO8_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO8_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO8_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO8_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO8_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO8_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO8_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO8_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO8_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO8_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO8_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO8_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO8_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO8_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO8_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO8_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO8_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO8_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO8_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO8_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO8_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO8_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO8_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO8_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO8_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO8_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO8_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO8_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO8_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO8_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO8_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO8_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO8_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_OFFSET: u32 = 40;
pub const PADS_BANK0_GPIO9_BITS: u32 = 255;
pub const PADS_BANK0_GPIO9_RESET: u32 = 86;
pub const PADS_BANK0_GPIO9_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO9_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO9_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO9_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO9_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO9_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO9_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO9_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO9_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO9_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO9_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO9_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO9_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO9_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO9_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO9_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO9_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO9_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO9_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO9_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO9_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO9_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO9_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO9_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO9_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO9_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO9_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO9_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO9_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO9_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO9_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO9_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO9_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO9_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_OFFSET: u32 = 44;
pub const PADS_BANK0_GPIO10_BITS: u32 = 255;
pub const PADS_BANK0_GPIO10_RESET: u32 = 86;
pub const PADS_BANK0_GPIO10_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO10_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO10_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO10_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO10_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO10_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO10_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO10_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO10_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO10_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO10_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO10_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO10_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO10_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO10_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO10_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO10_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO10_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO10_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO10_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO10_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO10_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO10_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO10_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO10_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO10_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO10_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO10_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO10_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO10_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO10_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO10_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO10_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO10_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_OFFSET: u32 = 48;
pub const PADS_BANK0_GPIO11_BITS: u32 = 255;
pub const PADS_BANK0_GPIO11_RESET: u32 = 86;
pub const PADS_BANK0_GPIO11_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO11_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO11_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO11_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO11_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO11_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO11_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO11_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO11_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO11_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO11_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO11_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO11_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO11_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO11_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO11_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO11_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO11_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO11_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO11_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO11_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO11_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO11_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO11_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO11_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO11_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO11_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO11_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO11_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO11_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO11_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO11_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO11_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO11_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_OFFSET: u32 = 52;
pub const PADS_BANK0_GPIO12_BITS: u32 = 255;
pub const PADS_BANK0_GPIO12_RESET: u32 = 86;
pub const PADS_BANK0_GPIO12_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO12_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO12_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO12_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO12_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO12_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO12_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO12_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO12_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO12_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO12_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO12_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO12_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO12_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO12_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO12_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO12_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO12_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO12_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO12_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO12_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO12_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO12_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO12_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO12_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO12_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO12_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO12_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO12_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO12_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO12_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO12_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO12_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO12_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_OFFSET: u32 = 56;
pub const PADS_BANK0_GPIO13_BITS: u32 = 255;
pub const PADS_BANK0_GPIO13_RESET: u32 = 86;
pub const PADS_BANK0_GPIO13_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO13_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO13_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO13_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO13_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO13_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO13_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO13_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO13_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO13_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO13_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO13_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO13_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO13_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO13_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO13_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO13_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO13_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO13_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO13_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO13_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO13_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO13_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO13_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO13_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO13_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO13_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO13_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO13_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO13_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO13_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO13_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO13_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO13_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_OFFSET: u32 = 60;
pub const PADS_BANK0_GPIO14_BITS: u32 = 255;
pub const PADS_BANK0_GPIO14_RESET: u32 = 86;
pub const PADS_BANK0_GPIO14_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO14_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO14_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO14_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO14_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO14_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO14_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO14_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO14_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO14_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO14_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO14_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO14_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO14_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO14_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO14_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO14_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO14_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO14_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO14_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO14_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO14_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO14_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO14_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO14_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO14_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO14_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO14_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO14_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO14_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO14_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO14_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO14_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO14_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_OFFSET: u32 = 64;
pub const PADS_BANK0_GPIO15_BITS: u32 = 255;
pub const PADS_BANK0_GPIO15_RESET: u32 = 86;
pub const PADS_BANK0_GPIO15_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO15_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO15_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO15_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO15_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO15_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO15_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO15_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO15_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO15_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO15_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO15_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO15_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO15_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO15_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO15_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO15_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO15_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO15_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO15_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO15_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO15_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO15_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO15_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO15_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO15_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO15_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO15_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO15_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO15_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO15_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO15_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO15_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO15_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_OFFSET: u32 = 68;
pub const PADS_BANK0_GPIO16_BITS: u32 = 255;
pub const PADS_BANK0_GPIO16_RESET: u32 = 86;
pub const PADS_BANK0_GPIO16_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO16_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO16_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO16_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO16_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO16_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO16_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO16_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO16_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO16_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO16_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO16_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO16_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO16_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO16_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO16_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO16_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO16_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO16_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO16_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO16_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO16_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO16_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO16_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO16_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO16_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO16_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO16_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO16_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO16_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO16_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO16_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO16_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO16_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_OFFSET: u32 = 72;
pub const PADS_BANK0_GPIO17_BITS: u32 = 255;
pub const PADS_BANK0_GPIO17_RESET: u32 = 86;
pub const PADS_BANK0_GPIO17_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO17_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO17_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO17_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO17_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO17_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO17_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO17_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO17_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO17_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO17_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO17_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO17_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO17_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO17_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO17_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO17_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO17_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO17_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO17_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO17_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO17_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO17_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO17_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO17_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO17_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO17_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO17_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO17_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO17_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO17_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO17_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO17_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO17_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_OFFSET: u32 = 76;
pub const PADS_BANK0_GPIO18_BITS: u32 = 255;
pub const PADS_BANK0_GPIO18_RESET: u32 = 86;
pub const PADS_BANK0_GPIO18_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO18_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO18_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO18_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO18_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO18_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO18_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO18_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO18_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO18_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO18_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO18_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO18_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO18_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO18_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO18_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO18_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO18_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO18_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO18_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO18_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO18_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO18_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO18_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO18_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO18_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO18_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO18_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO18_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO18_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO18_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO18_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO18_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO18_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_OFFSET: u32 = 80;
pub const PADS_BANK0_GPIO19_BITS: u32 = 255;
pub const PADS_BANK0_GPIO19_RESET: u32 = 86;
pub const PADS_BANK0_GPIO19_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO19_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO19_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO19_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO19_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO19_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO19_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO19_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO19_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO19_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO19_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO19_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO19_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO19_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO19_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO19_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO19_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO19_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO19_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO19_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO19_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO19_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO19_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO19_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO19_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO19_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO19_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO19_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO19_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO19_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO19_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO19_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO19_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO19_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_OFFSET: u32 = 84;
pub const PADS_BANK0_GPIO20_BITS: u32 = 255;
pub const PADS_BANK0_GPIO20_RESET: u32 = 86;
pub const PADS_BANK0_GPIO20_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO20_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO20_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO20_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO20_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO20_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO20_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO20_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO20_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO20_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO20_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO20_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO20_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO20_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO20_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO20_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO20_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO20_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO20_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO20_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO20_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO20_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO20_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO20_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO20_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO20_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO20_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO20_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO20_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO20_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO20_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO20_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO20_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO20_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_OFFSET: u32 = 88;
pub const PADS_BANK0_GPIO21_BITS: u32 = 255;
pub const PADS_BANK0_GPIO21_RESET: u32 = 86;
pub const PADS_BANK0_GPIO21_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO21_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO21_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO21_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO21_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO21_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO21_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO21_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO21_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO21_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO21_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO21_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO21_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO21_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO21_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO21_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO21_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO21_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO21_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO21_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO21_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO21_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO21_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO21_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO21_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO21_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO21_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO21_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO21_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO21_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO21_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO21_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO21_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO21_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_OFFSET: u32 = 92;
pub const PADS_BANK0_GPIO22_BITS: u32 = 255;
pub const PADS_BANK0_GPIO22_RESET: u32 = 86;
pub const PADS_BANK0_GPIO22_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO22_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO22_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO22_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO22_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO22_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO22_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO22_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO22_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO22_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO22_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO22_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO22_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO22_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO22_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO22_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO22_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO22_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO22_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO22_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO22_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO22_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO22_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO22_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO22_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO22_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO22_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO22_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO22_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO22_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO22_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO22_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO22_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO22_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_OFFSET: u32 = 96;
pub const PADS_BANK0_GPIO23_BITS: u32 = 255;
pub const PADS_BANK0_GPIO23_RESET: u32 = 86;
pub const PADS_BANK0_GPIO23_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO23_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO23_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO23_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO23_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO23_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO23_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO23_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO23_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO23_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO23_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO23_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO23_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO23_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO23_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO23_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO23_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO23_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO23_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO23_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO23_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO23_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO23_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO23_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO23_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO23_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO23_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO23_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO23_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO23_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO23_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO23_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO23_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO23_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_OFFSET: u32 = 100;
pub const PADS_BANK0_GPIO24_BITS: u32 = 255;
pub const PADS_BANK0_GPIO24_RESET: u32 = 86;
pub const PADS_BANK0_GPIO24_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO24_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO24_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO24_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO24_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO24_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO24_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO24_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO24_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO24_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO24_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO24_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO24_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO24_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO24_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO24_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO24_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO24_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO24_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO24_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO24_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO24_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO24_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO24_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO24_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO24_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO24_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO24_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO24_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO24_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO24_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO24_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO24_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO24_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_OFFSET: u32 = 104;
pub const PADS_BANK0_GPIO25_BITS: u32 = 255;
pub const PADS_BANK0_GPIO25_RESET: u32 = 86;
pub const PADS_BANK0_GPIO25_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO25_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO25_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO25_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO25_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO25_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO25_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO25_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO25_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO25_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO25_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO25_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO25_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO25_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO25_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO25_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO25_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO25_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO25_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO25_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO25_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO25_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO25_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO25_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO25_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO25_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO25_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO25_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO25_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO25_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO25_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO25_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO25_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO25_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_OFFSET: u32 = 108;
pub const PADS_BANK0_GPIO26_BITS: u32 = 255;
pub const PADS_BANK0_GPIO26_RESET: u32 = 86;
pub const PADS_BANK0_GPIO26_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO26_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO26_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO26_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO26_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO26_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO26_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO26_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO26_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO26_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO26_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO26_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO26_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO26_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO26_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO26_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO26_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO26_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO26_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO26_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO26_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO26_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO26_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO26_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO26_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO26_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO26_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO26_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO26_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO26_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO26_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO26_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO26_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO26_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_OFFSET: u32 = 112;
pub const PADS_BANK0_GPIO27_BITS: u32 = 255;
pub const PADS_BANK0_GPIO27_RESET: u32 = 86;
pub const PADS_BANK0_GPIO27_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO27_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO27_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO27_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO27_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO27_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO27_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO27_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO27_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO27_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO27_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO27_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO27_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO27_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO27_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO27_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO27_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO27_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO27_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO27_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO27_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO27_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO27_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO27_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO27_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO27_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO27_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO27_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO27_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO27_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO27_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO27_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO27_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO27_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_OFFSET: u32 = 116;
pub const PADS_BANK0_GPIO28_BITS: u32 = 255;
pub const PADS_BANK0_GPIO28_RESET: u32 = 86;
pub const PADS_BANK0_GPIO28_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO28_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO28_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO28_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO28_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO28_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO28_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO28_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO28_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO28_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO28_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO28_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO28_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO28_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO28_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO28_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO28_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO28_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO28_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO28_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO28_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO28_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO28_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO28_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO28_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO28_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO28_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO28_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO28_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO28_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO28_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO28_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO28_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO28_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_OFFSET: u32 = 120;
pub const PADS_BANK0_GPIO29_BITS: u32 = 255;
pub const PADS_BANK0_GPIO29_RESET: u32 = 86;
pub const PADS_BANK0_GPIO29_OD_RESET: u32 = 0;
pub const PADS_BANK0_GPIO29_OD_BITS: u32 = 128;
pub const PADS_BANK0_GPIO29_OD_MSB: u32 = 7;
pub const PADS_BANK0_GPIO29_OD_LSB: u32 = 7;
pub const PADS_BANK0_GPIO29_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_IE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO29_IE_BITS: u32 = 64;
pub const PADS_BANK0_GPIO29_IE_MSB: u32 = 6;
pub const PADS_BANK0_GPIO29_IE_LSB: u32 = 6;
pub const PADS_BANK0_GPIO29_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO29_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_GPIO29_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_GPIO29_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_GPIO29_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_GPIO29_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_GPIO29_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_GPIO29_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_GPIO29_PUE_RESET: u32 = 0;
pub const PADS_BANK0_GPIO29_PUE_BITS: u32 = 8;
pub const PADS_BANK0_GPIO29_PUE_MSB: u32 = 3;
pub const PADS_BANK0_GPIO29_PUE_LSB: u32 = 3;
pub const PADS_BANK0_GPIO29_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_PDE_RESET: u32 = 1;
pub const PADS_BANK0_GPIO29_PDE_BITS: u32 = 4;
pub const PADS_BANK0_GPIO29_PDE_MSB: u32 = 2;
pub const PADS_BANK0_GPIO29_PDE_LSB: u32 = 2;
pub const PADS_BANK0_GPIO29_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_GPIO29_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_GPIO29_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_GPIO29_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_GPIO29_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_GPIO29_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_GPIO29_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_GPIO29_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_GPIO29_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_GPIO29_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_OFFSET: u32 = 124;
pub const PADS_BANK0_SWCLK_BITS: u32 = 255;
pub const PADS_BANK0_SWCLK_RESET: u32 = 218;
pub const PADS_BANK0_SWCLK_OD_RESET: u32 = 1;
pub const PADS_BANK0_SWCLK_OD_BITS: u32 = 128;
pub const PADS_BANK0_SWCLK_OD_MSB: u32 = 7;
pub const PADS_BANK0_SWCLK_OD_LSB: u32 = 7;
pub const PADS_BANK0_SWCLK_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_IE_RESET: u32 = 1;
pub const PADS_BANK0_SWCLK_IE_BITS: u32 = 64;
pub const PADS_BANK0_SWCLK_IE_MSB: u32 = 6;
pub const PADS_BANK0_SWCLK_IE_LSB: u32 = 6;
pub const PADS_BANK0_SWCLK_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_SWCLK_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_SWCLK_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_SWCLK_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_SWCLK_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_SWCLK_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_SWCLK_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_SWCLK_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_SWCLK_PUE_RESET: u32 = 1;
pub const PADS_BANK0_SWCLK_PUE_BITS: u32 = 8;
pub const PADS_BANK0_SWCLK_PUE_MSB: u32 = 3;
pub const PADS_BANK0_SWCLK_PUE_LSB: u32 = 3;
pub const PADS_BANK0_SWCLK_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_PDE_RESET: u32 = 0;
pub const PADS_BANK0_SWCLK_PDE_BITS: u32 = 4;
pub const PADS_BANK0_SWCLK_PDE_MSB: u32 = 2;
pub const PADS_BANK0_SWCLK_PDE_LSB: u32 = 2;
pub const PADS_BANK0_SWCLK_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_SWCLK_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_SWCLK_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_SWCLK_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_SWCLK_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWCLK_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_SWCLK_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_SWCLK_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_SWCLK_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_SWCLK_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_OFFSET: u32 = 128;
pub const PADS_BANK0_SWD_BITS: u32 = 255;
pub const PADS_BANK0_SWD_RESET: u32 = 90;
pub const PADS_BANK0_SWD_OD_RESET: u32 = 0;
pub const PADS_BANK0_SWD_OD_BITS: u32 = 128;
pub const PADS_BANK0_SWD_OD_MSB: u32 = 7;
pub const PADS_BANK0_SWD_OD_LSB: u32 = 7;
pub const PADS_BANK0_SWD_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_IE_RESET: u32 = 1;
pub const PADS_BANK0_SWD_IE_BITS: u32 = 64;
pub const PADS_BANK0_SWD_IE_MSB: u32 = 6;
pub const PADS_BANK0_SWD_IE_LSB: u32 = 6;
pub const PADS_BANK0_SWD_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_DRIVE_RESET: u32 = 1;
pub const PADS_BANK0_SWD_DRIVE_BITS: u32 = 48;
pub const PADS_BANK0_SWD_DRIVE_MSB: u32 = 5;
pub const PADS_BANK0_SWD_DRIVE_LSB: u32 = 4;
pub const PADS_BANK0_SWD_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_DRIVE_VALUE_2MA: u32 = 0;
pub const PADS_BANK0_SWD_DRIVE_VALUE_4MA: u32 = 1;
pub const PADS_BANK0_SWD_DRIVE_VALUE_8MA: u32 = 2;
pub const PADS_BANK0_SWD_DRIVE_VALUE_12MA: u32 = 3;
pub const PADS_BANK0_SWD_PUE_RESET: u32 = 1;
pub const PADS_BANK0_SWD_PUE_BITS: u32 = 8;
pub const PADS_BANK0_SWD_PUE_MSB: u32 = 3;
pub const PADS_BANK0_SWD_PUE_LSB: u32 = 3;
pub const PADS_BANK0_SWD_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_PDE_RESET: u32 = 0;
pub const PADS_BANK0_SWD_PDE_BITS: u32 = 4;
pub const PADS_BANK0_SWD_PDE_MSB: u32 = 2;
pub const PADS_BANK0_SWD_PDE_LSB: u32 = 2;
pub const PADS_BANK0_SWD_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_SCHMITT_RESET: u32 = 1;
pub const PADS_BANK0_SWD_SCHMITT_BITS: u32 = 2;
pub const PADS_BANK0_SWD_SCHMITT_MSB: u32 = 1;
pub const PADS_BANK0_SWD_SCHMITT_LSB: u32 = 1;
pub const PADS_BANK0_SWD_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PADS_BANK0_SWD_SLEWFAST_RESET: u32 = 0;
pub const PADS_BANK0_SWD_SLEWFAST_BITS: u32 = 1;
pub const PADS_BANK0_SWD_SLEWFAST_MSB: u32 = 0;
pub const PADS_BANK0_SWD_SLEWFAST_LSB: u32 = 0;
pub const PADS_BANK0_SWD_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const PARAM_ASSERTIONS_ENABLED_GPIO: u32 = 0;
pub const GPIO_OUT: u32 = 1;
pub const GPIO_IN: u32 = 0;
pub const N_GPIOS: u32 = 30;
pub const PICO_DEBUG_PIN_BASE: u32 = 19;
pub const PICO_DEBUG_PIN_COUNT: u32 = 3;
pub const UART_UARTDR_OFFSET: u32 = 0;
pub const UART_UARTDR_BITS: u32 = 4095;
pub const UART_UARTDR_RESET: u32 = 0;
pub const UART_UARTDR_OE_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTDR_OE_BITS: u32 = 2048;
pub const UART_UARTDR_OE_MSB: u32 = 11;
pub const UART_UARTDR_OE_LSB: u32 = 11;
pub const UART_UARTDR_OE_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTDR_BE_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTDR_BE_BITS: u32 = 1024;
pub const UART_UARTDR_BE_MSB: u32 = 10;
pub const UART_UARTDR_BE_LSB: u32 = 10;
pub const UART_UARTDR_BE_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTDR_PE_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTDR_PE_BITS: u32 = 512;
pub const UART_UARTDR_PE_MSB: u32 = 9;
pub const UART_UARTDR_PE_LSB: u32 = 9;
pub const UART_UARTDR_PE_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTDR_FE_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTDR_FE_BITS: u32 = 256;
pub const UART_UARTDR_FE_MSB: u32 = 8;
pub const UART_UARTDR_FE_LSB: u32 = 8;
pub const UART_UARTDR_FE_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTDR_DATA_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTDR_DATA_BITS: u32 = 255;
pub const UART_UARTDR_DATA_MSB: u32 = 7;
pub const UART_UARTDR_DATA_LSB: u32 = 0;
pub const UART_UARTDR_DATA_ACCESS: &'static [u8; 4usize] = b"RWF\0";
pub const UART_UARTRSR_OFFSET: u32 = 4;
pub const UART_UARTRSR_BITS: u32 = 15;
pub const UART_UARTRSR_RESET: u32 = 0;
pub const UART_UARTRSR_OE_RESET: u32 = 0;
pub const UART_UARTRSR_OE_BITS: u32 = 8;
pub const UART_UARTRSR_OE_MSB: u32 = 3;
pub const UART_UARTRSR_OE_LSB: u32 = 3;
pub const UART_UARTRSR_OE_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTRSR_BE_RESET: u32 = 0;
pub const UART_UARTRSR_BE_BITS: u32 = 4;
pub const UART_UARTRSR_BE_MSB: u32 = 2;
pub const UART_UARTRSR_BE_LSB: u32 = 2;
pub const UART_UARTRSR_BE_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTRSR_PE_RESET: u32 = 0;
pub const UART_UARTRSR_PE_BITS: u32 = 2;
pub const UART_UARTRSR_PE_MSB: u32 = 1;
pub const UART_UARTRSR_PE_LSB: u32 = 1;
pub const UART_UARTRSR_PE_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTRSR_FE_RESET: u32 = 0;
pub const UART_UARTRSR_FE_BITS: u32 = 1;
pub const UART_UARTRSR_FE_MSB: u32 = 0;
pub const UART_UARTRSR_FE_LSB: u32 = 0;
pub const UART_UARTRSR_FE_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTFR_OFFSET: u32 = 24;
pub const UART_UARTFR_BITS: u32 = 511;
pub const UART_UARTFR_RESET: u32 = 144;
pub const UART_UARTFR_RI_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTFR_RI_BITS: u32 = 256;
pub const UART_UARTFR_RI_MSB: u32 = 8;
pub const UART_UARTFR_RI_LSB: u32 = 8;
pub const UART_UARTFR_RI_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_TXFE_RESET: u32 = 1;
pub const UART_UARTFR_TXFE_BITS: u32 = 128;
pub const UART_UARTFR_TXFE_MSB: u32 = 7;
pub const UART_UARTFR_TXFE_LSB: u32 = 7;
pub const UART_UARTFR_TXFE_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_RXFF_RESET: u32 = 0;
pub const UART_UARTFR_RXFF_BITS: u32 = 64;
pub const UART_UARTFR_RXFF_MSB: u32 = 6;
pub const UART_UARTFR_RXFF_LSB: u32 = 6;
pub const UART_UARTFR_RXFF_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_TXFF_RESET: u32 = 0;
pub const UART_UARTFR_TXFF_BITS: u32 = 32;
pub const UART_UARTFR_TXFF_MSB: u32 = 5;
pub const UART_UARTFR_TXFF_LSB: u32 = 5;
pub const UART_UARTFR_TXFF_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_RXFE_RESET: u32 = 1;
pub const UART_UARTFR_RXFE_BITS: u32 = 16;
pub const UART_UARTFR_RXFE_MSB: u32 = 4;
pub const UART_UARTFR_RXFE_LSB: u32 = 4;
pub const UART_UARTFR_RXFE_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_BUSY_RESET: u32 = 0;
pub const UART_UARTFR_BUSY_BITS: u32 = 8;
pub const UART_UARTFR_BUSY_MSB: u32 = 3;
pub const UART_UARTFR_BUSY_LSB: u32 = 3;
pub const UART_UARTFR_BUSY_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_DCD_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTFR_DCD_BITS: u32 = 4;
pub const UART_UARTFR_DCD_MSB: u32 = 2;
pub const UART_UARTFR_DCD_LSB: u32 = 2;
pub const UART_UARTFR_DCD_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_DSR_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTFR_DSR_BITS: u32 = 2;
pub const UART_UARTFR_DSR_MSB: u32 = 1;
pub const UART_UARTFR_DSR_LSB: u32 = 1;
pub const UART_UARTFR_DSR_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTFR_CTS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTFR_CTS_BITS: u32 = 1;
pub const UART_UARTFR_CTS_MSB: u32 = 0;
pub const UART_UARTFR_CTS_LSB: u32 = 0;
pub const UART_UARTFR_CTS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTILPR_OFFSET: u32 = 32;
pub const UART_UARTILPR_BITS: u32 = 255;
pub const UART_UARTILPR_RESET: u32 = 0;
pub const UART_UARTILPR_ILPDVSR_RESET: u32 = 0;
pub const UART_UARTILPR_ILPDVSR_BITS: u32 = 255;
pub const UART_UARTILPR_ILPDVSR_MSB: u32 = 7;
pub const UART_UARTILPR_ILPDVSR_LSB: u32 = 0;
pub const UART_UARTILPR_ILPDVSR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIBRD_OFFSET: u32 = 36;
pub const UART_UARTIBRD_BITS: u32 = 65535;
pub const UART_UARTIBRD_RESET: u32 = 0;
pub const UART_UARTIBRD_BAUD_DIVINT_RESET: u32 = 0;
pub const UART_UARTIBRD_BAUD_DIVINT_BITS: u32 = 65535;
pub const UART_UARTIBRD_BAUD_DIVINT_MSB: u32 = 15;
pub const UART_UARTIBRD_BAUD_DIVINT_LSB: u32 = 0;
pub const UART_UARTIBRD_BAUD_DIVINT_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTFBRD_OFFSET: u32 = 40;
pub const UART_UARTFBRD_BITS: u32 = 63;
pub const UART_UARTFBRD_RESET: u32 = 0;
pub const UART_UARTFBRD_BAUD_DIVFRAC_RESET: u32 = 0;
pub const UART_UARTFBRD_BAUD_DIVFRAC_BITS: u32 = 63;
pub const UART_UARTFBRD_BAUD_DIVFRAC_MSB: u32 = 5;
pub const UART_UARTFBRD_BAUD_DIVFRAC_LSB: u32 = 0;
pub const UART_UARTFBRD_BAUD_DIVFRAC_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_OFFSET: u32 = 44;
pub const UART_UARTLCR_H_BITS: u32 = 255;
pub const UART_UARTLCR_H_RESET: u32 = 0;
pub const UART_UARTLCR_H_SPS_RESET: u32 = 0;
pub const UART_UARTLCR_H_SPS_BITS: u32 = 128;
pub const UART_UARTLCR_H_SPS_MSB: u32 = 7;
pub const UART_UARTLCR_H_SPS_LSB: u32 = 7;
pub const UART_UARTLCR_H_SPS_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_WLEN_RESET: u32 = 0;
pub const UART_UARTLCR_H_WLEN_BITS: u32 = 96;
pub const UART_UARTLCR_H_WLEN_MSB: u32 = 6;
pub const UART_UARTLCR_H_WLEN_LSB: u32 = 5;
pub const UART_UARTLCR_H_WLEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_FEN_RESET: u32 = 0;
pub const UART_UARTLCR_H_FEN_BITS: u32 = 16;
pub const UART_UARTLCR_H_FEN_MSB: u32 = 4;
pub const UART_UARTLCR_H_FEN_LSB: u32 = 4;
pub const UART_UARTLCR_H_FEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_STP2_RESET: u32 = 0;
pub const UART_UARTLCR_H_STP2_BITS: u32 = 8;
pub const UART_UARTLCR_H_STP2_MSB: u32 = 3;
pub const UART_UARTLCR_H_STP2_LSB: u32 = 3;
pub const UART_UARTLCR_H_STP2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_EPS_RESET: u32 = 0;
pub const UART_UARTLCR_H_EPS_BITS: u32 = 4;
pub const UART_UARTLCR_H_EPS_MSB: u32 = 2;
pub const UART_UARTLCR_H_EPS_LSB: u32 = 2;
pub const UART_UARTLCR_H_EPS_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_PEN_RESET: u32 = 0;
pub const UART_UARTLCR_H_PEN_BITS: u32 = 2;
pub const UART_UARTLCR_H_PEN_MSB: u32 = 1;
pub const UART_UARTLCR_H_PEN_LSB: u32 = 1;
pub const UART_UARTLCR_H_PEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTLCR_H_BRK_RESET: u32 = 0;
pub const UART_UARTLCR_H_BRK_BITS: u32 = 1;
pub const UART_UARTLCR_H_BRK_MSB: u32 = 0;
pub const UART_UARTLCR_H_BRK_LSB: u32 = 0;
pub const UART_UARTLCR_H_BRK_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_OFFSET: u32 = 48;
pub const UART_UARTCR_BITS: u32 = 65415;
pub const UART_UARTCR_RESET: u32 = 768;
pub const UART_UARTCR_CTSEN_RESET: u32 = 0;
pub const UART_UARTCR_CTSEN_BITS: u32 = 32768;
pub const UART_UARTCR_CTSEN_MSB: u32 = 15;
pub const UART_UARTCR_CTSEN_LSB: u32 = 15;
pub const UART_UARTCR_CTSEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_RTSEN_RESET: u32 = 0;
pub const UART_UARTCR_RTSEN_BITS: u32 = 16384;
pub const UART_UARTCR_RTSEN_MSB: u32 = 14;
pub const UART_UARTCR_RTSEN_LSB: u32 = 14;
pub const UART_UARTCR_RTSEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_OUT2_RESET: u32 = 0;
pub const UART_UARTCR_OUT2_BITS: u32 = 8192;
pub const UART_UARTCR_OUT2_MSB: u32 = 13;
pub const UART_UARTCR_OUT2_LSB: u32 = 13;
pub const UART_UARTCR_OUT2_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_OUT1_RESET: u32 = 0;
pub const UART_UARTCR_OUT1_BITS: u32 = 4096;
pub const UART_UARTCR_OUT1_MSB: u32 = 12;
pub const UART_UARTCR_OUT1_LSB: u32 = 12;
pub const UART_UARTCR_OUT1_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_RTS_RESET: u32 = 0;
pub const UART_UARTCR_RTS_BITS: u32 = 2048;
pub const UART_UARTCR_RTS_MSB: u32 = 11;
pub const UART_UARTCR_RTS_LSB: u32 = 11;
pub const UART_UARTCR_RTS_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_DTR_RESET: u32 = 0;
pub const UART_UARTCR_DTR_BITS: u32 = 1024;
pub const UART_UARTCR_DTR_MSB: u32 = 10;
pub const UART_UARTCR_DTR_LSB: u32 = 10;
pub const UART_UARTCR_DTR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_RXE_RESET: u32 = 1;
pub const UART_UARTCR_RXE_BITS: u32 = 512;
pub const UART_UARTCR_RXE_MSB: u32 = 9;
pub const UART_UARTCR_RXE_LSB: u32 = 9;
pub const UART_UARTCR_RXE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_TXE_RESET: u32 = 1;
pub const UART_UARTCR_TXE_BITS: u32 = 256;
pub const UART_UARTCR_TXE_MSB: u32 = 8;
pub const UART_UARTCR_TXE_LSB: u32 = 8;
pub const UART_UARTCR_TXE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_LBE_RESET: u32 = 0;
pub const UART_UARTCR_LBE_BITS: u32 = 128;
pub const UART_UARTCR_LBE_MSB: u32 = 7;
pub const UART_UARTCR_LBE_LSB: u32 = 7;
pub const UART_UARTCR_LBE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_SIRLP_RESET: u32 = 0;
pub const UART_UARTCR_SIRLP_BITS: u32 = 4;
pub const UART_UARTCR_SIRLP_MSB: u32 = 2;
pub const UART_UARTCR_SIRLP_LSB: u32 = 2;
pub const UART_UARTCR_SIRLP_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_SIREN_RESET: u32 = 0;
pub const UART_UARTCR_SIREN_BITS: u32 = 2;
pub const UART_UARTCR_SIREN_MSB: u32 = 1;
pub const UART_UARTCR_SIREN_LSB: u32 = 1;
pub const UART_UARTCR_SIREN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTCR_UARTEN_RESET: u32 = 0;
pub const UART_UARTCR_UARTEN_BITS: u32 = 1;
pub const UART_UARTCR_UARTEN_MSB: u32 = 0;
pub const UART_UARTCR_UARTEN_LSB: u32 = 0;
pub const UART_UARTCR_UARTEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIFLS_OFFSET: u32 = 52;
pub const UART_UARTIFLS_BITS: u32 = 63;
pub const UART_UARTIFLS_RESET: u32 = 18;
pub const UART_UARTIFLS_RXIFLSEL_RESET: u32 = 2;
pub const UART_UARTIFLS_RXIFLSEL_BITS: u32 = 56;
pub const UART_UARTIFLS_RXIFLSEL_MSB: u32 = 5;
pub const UART_UARTIFLS_RXIFLSEL_LSB: u32 = 3;
pub const UART_UARTIFLS_RXIFLSEL_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIFLS_TXIFLSEL_RESET: u32 = 2;
pub const UART_UARTIFLS_TXIFLSEL_BITS: u32 = 7;
pub const UART_UARTIFLS_TXIFLSEL_MSB: u32 = 2;
pub const UART_UARTIFLS_TXIFLSEL_LSB: u32 = 0;
pub const UART_UARTIFLS_TXIFLSEL_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_OFFSET: u32 = 56;
pub const UART_UARTIMSC_BITS: u32 = 2047;
pub const UART_UARTIMSC_RESET: u32 = 0;
pub const UART_UARTIMSC_OEIM_RESET: u32 = 0;
pub const UART_UARTIMSC_OEIM_BITS: u32 = 1024;
pub const UART_UARTIMSC_OEIM_MSB: u32 = 10;
pub const UART_UARTIMSC_OEIM_LSB: u32 = 10;
pub const UART_UARTIMSC_OEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_BEIM_RESET: u32 = 0;
pub const UART_UARTIMSC_BEIM_BITS: u32 = 512;
pub const UART_UARTIMSC_BEIM_MSB: u32 = 9;
pub const UART_UARTIMSC_BEIM_LSB: u32 = 9;
pub const UART_UARTIMSC_BEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_PEIM_RESET: u32 = 0;
pub const UART_UARTIMSC_PEIM_BITS: u32 = 256;
pub const UART_UARTIMSC_PEIM_MSB: u32 = 8;
pub const UART_UARTIMSC_PEIM_LSB: u32 = 8;
pub const UART_UARTIMSC_PEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_FEIM_RESET: u32 = 0;
pub const UART_UARTIMSC_FEIM_BITS: u32 = 128;
pub const UART_UARTIMSC_FEIM_MSB: u32 = 7;
pub const UART_UARTIMSC_FEIM_LSB: u32 = 7;
pub const UART_UARTIMSC_FEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_RTIM_RESET: u32 = 0;
pub const UART_UARTIMSC_RTIM_BITS: u32 = 64;
pub const UART_UARTIMSC_RTIM_MSB: u32 = 6;
pub const UART_UARTIMSC_RTIM_LSB: u32 = 6;
pub const UART_UARTIMSC_RTIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_TXIM_RESET: u32 = 0;
pub const UART_UARTIMSC_TXIM_BITS: u32 = 32;
pub const UART_UARTIMSC_TXIM_MSB: u32 = 5;
pub const UART_UARTIMSC_TXIM_LSB: u32 = 5;
pub const UART_UARTIMSC_TXIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_RXIM_RESET: u32 = 0;
pub const UART_UARTIMSC_RXIM_BITS: u32 = 16;
pub const UART_UARTIMSC_RXIM_MSB: u32 = 4;
pub const UART_UARTIMSC_RXIM_LSB: u32 = 4;
pub const UART_UARTIMSC_RXIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_DSRMIM_RESET: u32 = 0;
pub const UART_UARTIMSC_DSRMIM_BITS: u32 = 8;
pub const UART_UARTIMSC_DSRMIM_MSB: u32 = 3;
pub const UART_UARTIMSC_DSRMIM_LSB: u32 = 3;
pub const UART_UARTIMSC_DSRMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_DCDMIM_RESET: u32 = 0;
pub const UART_UARTIMSC_DCDMIM_BITS: u32 = 4;
pub const UART_UARTIMSC_DCDMIM_MSB: u32 = 2;
pub const UART_UARTIMSC_DCDMIM_LSB: u32 = 2;
pub const UART_UARTIMSC_DCDMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_CTSMIM_RESET: u32 = 0;
pub const UART_UARTIMSC_CTSMIM_BITS: u32 = 2;
pub const UART_UARTIMSC_CTSMIM_MSB: u32 = 1;
pub const UART_UARTIMSC_CTSMIM_LSB: u32 = 1;
pub const UART_UARTIMSC_CTSMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTIMSC_RIMIM_RESET: u32 = 0;
pub const UART_UARTIMSC_RIMIM_BITS: u32 = 1;
pub const UART_UARTIMSC_RIMIM_MSB: u32 = 0;
pub const UART_UARTIMSC_RIMIM_LSB: u32 = 0;
pub const UART_UARTIMSC_RIMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTRIS_OFFSET: u32 = 60;
pub const UART_UARTRIS_BITS: u32 = 2047;
pub const UART_UARTRIS_RESET: u32 = 0;
pub const UART_UARTRIS_OERIS_RESET: u32 = 0;
pub const UART_UARTRIS_OERIS_BITS: u32 = 1024;
pub const UART_UARTRIS_OERIS_MSB: u32 = 10;
pub const UART_UARTRIS_OERIS_LSB: u32 = 10;
pub const UART_UARTRIS_OERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_BERIS_RESET: u32 = 0;
pub const UART_UARTRIS_BERIS_BITS: u32 = 512;
pub const UART_UARTRIS_BERIS_MSB: u32 = 9;
pub const UART_UARTRIS_BERIS_LSB: u32 = 9;
pub const UART_UARTRIS_BERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_PERIS_RESET: u32 = 0;
pub const UART_UARTRIS_PERIS_BITS: u32 = 256;
pub const UART_UARTRIS_PERIS_MSB: u32 = 8;
pub const UART_UARTRIS_PERIS_LSB: u32 = 8;
pub const UART_UARTRIS_PERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_FERIS_RESET: u32 = 0;
pub const UART_UARTRIS_FERIS_BITS: u32 = 128;
pub const UART_UARTRIS_FERIS_MSB: u32 = 7;
pub const UART_UARTRIS_FERIS_LSB: u32 = 7;
pub const UART_UARTRIS_FERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_RTRIS_RESET: u32 = 0;
pub const UART_UARTRIS_RTRIS_BITS: u32 = 64;
pub const UART_UARTRIS_RTRIS_MSB: u32 = 6;
pub const UART_UARTRIS_RTRIS_LSB: u32 = 6;
pub const UART_UARTRIS_RTRIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_TXRIS_RESET: u32 = 0;
pub const UART_UARTRIS_TXRIS_BITS: u32 = 32;
pub const UART_UARTRIS_TXRIS_MSB: u32 = 5;
pub const UART_UARTRIS_TXRIS_LSB: u32 = 5;
pub const UART_UARTRIS_TXRIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_RXRIS_RESET: u32 = 0;
pub const UART_UARTRIS_RXRIS_BITS: u32 = 16;
pub const UART_UARTRIS_RXRIS_MSB: u32 = 4;
pub const UART_UARTRIS_RXRIS_LSB: u32 = 4;
pub const UART_UARTRIS_RXRIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_DSRRMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTRIS_DSRRMIS_BITS: u32 = 8;
pub const UART_UARTRIS_DSRRMIS_MSB: u32 = 3;
pub const UART_UARTRIS_DSRRMIS_LSB: u32 = 3;
pub const UART_UARTRIS_DSRRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_DCDRMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTRIS_DCDRMIS_BITS: u32 = 4;
pub const UART_UARTRIS_DCDRMIS_MSB: u32 = 2;
pub const UART_UARTRIS_DCDRMIS_LSB: u32 = 2;
pub const UART_UARTRIS_DCDRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_CTSRMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTRIS_CTSRMIS_BITS: u32 = 2;
pub const UART_UARTRIS_CTSRMIS_MSB: u32 = 1;
pub const UART_UARTRIS_CTSRMIS_LSB: u32 = 1;
pub const UART_UARTRIS_CTSRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTRIS_RIRMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTRIS_RIRMIS_BITS: u32 = 1;
pub const UART_UARTRIS_RIRMIS_MSB: u32 = 0;
pub const UART_UARTRIS_RIRMIS_LSB: u32 = 0;
pub const UART_UARTRIS_RIRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_OFFSET: u32 = 64;
pub const UART_UARTMIS_BITS: u32 = 2047;
pub const UART_UARTMIS_RESET: u32 = 0;
pub const UART_UARTMIS_OEMIS_RESET: u32 = 0;
pub const UART_UARTMIS_OEMIS_BITS: u32 = 1024;
pub const UART_UARTMIS_OEMIS_MSB: u32 = 10;
pub const UART_UARTMIS_OEMIS_LSB: u32 = 10;
pub const UART_UARTMIS_OEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_BEMIS_RESET: u32 = 0;
pub const UART_UARTMIS_BEMIS_BITS: u32 = 512;
pub const UART_UARTMIS_BEMIS_MSB: u32 = 9;
pub const UART_UARTMIS_BEMIS_LSB: u32 = 9;
pub const UART_UARTMIS_BEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_PEMIS_RESET: u32 = 0;
pub const UART_UARTMIS_PEMIS_BITS: u32 = 256;
pub const UART_UARTMIS_PEMIS_MSB: u32 = 8;
pub const UART_UARTMIS_PEMIS_LSB: u32 = 8;
pub const UART_UARTMIS_PEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_FEMIS_RESET: u32 = 0;
pub const UART_UARTMIS_FEMIS_BITS: u32 = 128;
pub const UART_UARTMIS_FEMIS_MSB: u32 = 7;
pub const UART_UARTMIS_FEMIS_LSB: u32 = 7;
pub const UART_UARTMIS_FEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_RTMIS_RESET: u32 = 0;
pub const UART_UARTMIS_RTMIS_BITS: u32 = 64;
pub const UART_UARTMIS_RTMIS_MSB: u32 = 6;
pub const UART_UARTMIS_RTMIS_LSB: u32 = 6;
pub const UART_UARTMIS_RTMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_TXMIS_RESET: u32 = 0;
pub const UART_UARTMIS_TXMIS_BITS: u32 = 32;
pub const UART_UARTMIS_TXMIS_MSB: u32 = 5;
pub const UART_UARTMIS_TXMIS_LSB: u32 = 5;
pub const UART_UARTMIS_TXMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_RXMIS_RESET: u32 = 0;
pub const UART_UARTMIS_RXMIS_BITS: u32 = 16;
pub const UART_UARTMIS_RXMIS_MSB: u32 = 4;
pub const UART_UARTMIS_RXMIS_LSB: u32 = 4;
pub const UART_UARTMIS_RXMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_DSRMMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTMIS_DSRMMIS_BITS: u32 = 8;
pub const UART_UARTMIS_DSRMMIS_MSB: u32 = 3;
pub const UART_UARTMIS_DSRMMIS_LSB: u32 = 3;
pub const UART_UARTMIS_DSRMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_DCDMMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTMIS_DCDMMIS_BITS: u32 = 4;
pub const UART_UARTMIS_DCDMMIS_MSB: u32 = 2;
pub const UART_UARTMIS_DCDMMIS_LSB: u32 = 2;
pub const UART_UARTMIS_DCDMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_CTSMMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTMIS_CTSMMIS_BITS: u32 = 2;
pub const UART_UARTMIS_CTSMMIS_MSB: u32 = 1;
pub const UART_UARTMIS_CTSMMIS_LSB: u32 = 1;
pub const UART_UARTMIS_CTSMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTMIS_RIMMIS_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTMIS_RIMMIS_BITS: u32 = 1;
pub const UART_UARTMIS_RIMMIS_MSB: u32 = 0;
pub const UART_UARTMIS_RIMMIS_LSB: u32 = 0;
pub const UART_UARTMIS_RIMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTICR_OFFSET: u32 = 68;
pub const UART_UARTICR_BITS: u32 = 2047;
pub const UART_UARTICR_RESET: u32 = 0;
pub const UART_UARTICR_OEIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_OEIC_BITS: u32 = 1024;
pub const UART_UARTICR_OEIC_MSB: u32 = 10;
pub const UART_UARTICR_OEIC_LSB: u32 = 10;
pub const UART_UARTICR_OEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_BEIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_BEIC_BITS: u32 = 512;
pub const UART_UARTICR_BEIC_MSB: u32 = 9;
pub const UART_UARTICR_BEIC_LSB: u32 = 9;
pub const UART_UARTICR_BEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_PEIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_PEIC_BITS: u32 = 256;
pub const UART_UARTICR_PEIC_MSB: u32 = 8;
pub const UART_UARTICR_PEIC_LSB: u32 = 8;
pub const UART_UARTICR_PEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_FEIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_FEIC_BITS: u32 = 128;
pub const UART_UARTICR_FEIC_MSB: u32 = 7;
pub const UART_UARTICR_FEIC_LSB: u32 = 7;
pub const UART_UARTICR_FEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_RTIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_RTIC_BITS: u32 = 64;
pub const UART_UARTICR_RTIC_MSB: u32 = 6;
pub const UART_UARTICR_RTIC_LSB: u32 = 6;
pub const UART_UARTICR_RTIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_TXIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_TXIC_BITS: u32 = 32;
pub const UART_UARTICR_TXIC_MSB: u32 = 5;
pub const UART_UARTICR_TXIC_LSB: u32 = 5;
pub const UART_UARTICR_TXIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_RXIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_RXIC_BITS: u32 = 16;
pub const UART_UARTICR_RXIC_MSB: u32 = 4;
pub const UART_UARTICR_RXIC_LSB: u32 = 4;
pub const UART_UARTICR_RXIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_DSRMIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_DSRMIC_BITS: u32 = 8;
pub const UART_UARTICR_DSRMIC_MSB: u32 = 3;
pub const UART_UARTICR_DSRMIC_LSB: u32 = 3;
pub const UART_UARTICR_DSRMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_DCDMIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_DCDMIC_BITS: u32 = 4;
pub const UART_UARTICR_DCDMIC_MSB: u32 = 2;
pub const UART_UARTICR_DCDMIC_LSB: u32 = 2;
pub const UART_UARTICR_DCDMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_CTSMIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_CTSMIC_BITS: u32 = 2;
pub const UART_UARTICR_CTSMIC_MSB: u32 = 1;
pub const UART_UARTICR_CTSMIC_LSB: u32 = 1;
pub const UART_UARTICR_CTSMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTICR_RIMIC_RESET: &'static [u8; 2usize] = b"-\0";
pub const UART_UARTICR_RIMIC_BITS: u32 = 1;
pub const UART_UARTICR_RIMIC_MSB: u32 = 0;
pub const UART_UARTICR_RIMIC_LSB: u32 = 0;
pub const UART_UARTICR_RIMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
pub const UART_UARTDMACR_OFFSET: u32 = 72;
pub const UART_UARTDMACR_BITS: u32 = 7;
pub const UART_UARTDMACR_RESET: u32 = 0;
pub const UART_UARTDMACR_DMAONERR_RESET: u32 = 0;
pub const UART_UARTDMACR_DMAONERR_BITS: u32 = 4;
pub const UART_UARTDMACR_DMAONERR_MSB: u32 = 2;
pub const UART_UARTDMACR_DMAONERR_LSB: u32 = 2;
pub const UART_UARTDMACR_DMAONERR_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTDMACR_TXDMAE_RESET: u32 = 0;
pub const UART_UARTDMACR_TXDMAE_BITS: u32 = 2;
pub const UART_UARTDMACR_TXDMAE_MSB: u32 = 1;
pub const UART_UARTDMACR_TXDMAE_LSB: u32 = 1;
pub const UART_UARTDMACR_TXDMAE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTDMACR_RXDMAE_RESET: u32 = 0;
pub const UART_UARTDMACR_RXDMAE_BITS: u32 = 1;
pub const UART_UARTDMACR_RXDMAE_MSB: u32 = 0;
pub const UART_UARTDMACR_RXDMAE_LSB: u32 = 0;
pub const UART_UARTDMACR_RXDMAE_ACCESS: &'static [u8; 3usize] = b"RW\0";
pub const UART_UARTPERIPHID0_OFFSET: u32 = 4064;
pub const UART_UARTPERIPHID0_BITS: u32 = 255;
pub const UART_UARTPERIPHID0_RESET: u32 = 17;
pub const UART_UARTPERIPHID0_PARTNUMBER0_RESET: u32 = 17;
pub const UART_UARTPERIPHID0_PARTNUMBER0_BITS: u32 = 255;
pub const UART_UARTPERIPHID0_PARTNUMBER0_MSB: u32 = 7;
pub const UART_UARTPERIPHID0_PARTNUMBER0_LSB: u32 = 0;
pub const UART_UARTPERIPHID0_PARTNUMBER0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPERIPHID1_OFFSET: u32 = 4068;
pub const UART_UARTPERIPHID1_BITS: u32 = 255;
pub const UART_UARTPERIPHID1_RESET: u32 = 16;
pub const UART_UARTPERIPHID1_DESIGNER0_RESET: u32 = 1;
pub const UART_UARTPERIPHID1_DESIGNER0_BITS: u32 = 240;
pub const UART_UARTPERIPHID1_DESIGNER0_MSB: u32 = 7;
pub const UART_UARTPERIPHID1_DESIGNER0_LSB: u32 = 4;
pub const UART_UARTPERIPHID1_DESIGNER0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPERIPHID1_PARTNUMBER1_RESET: u32 = 0;
pub const UART_UARTPERIPHID1_PARTNUMBER1_BITS: u32 = 15;
pub const UART_UARTPERIPHID1_PARTNUMBER1_MSB: u32 = 3;
pub const UART_UARTPERIPHID1_PARTNUMBER1_LSB: u32 = 0;
pub const UART_UARTPERIPHID1_PARTNUMBER1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPERIPHID2_OFFSET: u32 = 4072;
pub const UART_UARTPERIPHID2_BITS: u32 = 255;
pub const UART_UARTPERIPHID2_RESET: u32 = 52;
pub const UART_UARTPERIPHID2_REVISION_RESET: u32 = 3;
pub const UART_UARTPERIPHID2_REVISION_BITS: u32 = 240;
pub const UART_UARTPERIPHID2_REVISION_MSB: u32 = 7;
pub const UART_UARTPERIPHID2_REVISION_LSB: u32 = 4;
pub const UART_UARTPERIPHID2_REVISION_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPERIPHID2_DESIGNER1_RESET: u32 = 4;
pub const UART_UARTPERIPHID2_DESIGNER1_BITS: u32 = 15;
pub const UART_UARTPERIPHID2_DESIGNER1_MSB: u32 = 3;
pub const UART_UARTPERIPHID2_DESIGNER1_LSB: u32 = 0;
pub const UART_UARTPERIPHID2_DESIGNER1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPERIPHID3_OFFSET: u32 = 4076;
pub const UART_UARTPERIPHID3_BITS: u32 = 255;
pub const UART_UARTPERIPHID3_RESET: u32 = 0;
pub const UART_UARTPERIPHID3_CONFIGURATION_RESET: u32 = 0;
pub const UART_UARTPERIPHID3_CONFIGURATION_BITS: u32 = 255;
pub const UART_UARTPERIPHID3_CONFIGURATION_MSB: u32 = 7;
pub const UART_UARTPERIPHID3_CONFIGURATION_LSB: u32 = 0;
pub const UART_UARTPERIPHID3_CONFIGURATION_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPCELLID0_OFFSET: u32 = 4080;
pub const UART_UARTPCELLID0_BITS: u32 = 255;
pub const UART_UARTPCELLID0_RESET: u32 = 13;
pub const UART_UARTPCELLID0_UARTPCELLID0_RESET: u32 = 13;
pub const UART_UARTPCELLID0_UARTPCELLID0_BITS: u32 = 255;
pub const UART_UARTPCELLID0_UARTPCELLID0_MSB: u32 = 7;
pub const UART_UARTPCELLID0_UARTPCELLID0_LSB: u32 = 0;
pub const UART_UARTPCELLID0_UARTPCELLID0_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPCELLID1_OFFSET: u32 = 4084;
pub const UART_UARTPCELLID1_BITS: u32 = 255;
pub const UART_UARTPCELLID1_RESET: u32 = 240;
pub const UART_UARTPCELLID1_UARTPCELLID1_RESET: u32 = 240;
pub const UART_UARTPCELLID1_UARTPCELLID1_BITS: u32 = 255;
pub const UART_UARTPCELLID1_UARTPCELLID1_MSB: u32 = 7;
pub const UART_UARTPCELLID1_UARTPCELLID1_LSB: u32 = 0;
pub const UART_UARTPCELLID1_UARTPCELLID1_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPCELLID2_OFFSET: u32 = 4088;
pub const UART_UARTPCELLID2_BITS: u32 = 255;
pub const UART_UARTPCELLID2_RESET: u32 = 5;
pub const UART_UARTPCELLID2_UARTPCELLID2_RESET: u32 = 5;
pub const UART_UARTPCELLID2_UARTPCELLID2_BITS: u32 = 255;
pub const UART_UARTPCELLID2_UARTPCELLID2_MSB: u32 = 7;
pub const UART_UARTPCELLID2_UARTPCELLID2_LSB: u32 = 0;
pub const UART_UARTPCELLID2_UARTPCELLID2_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const UART_UARTPCELLID3_OFFSET: u32 = 4092;
pub const UART_UARTPCELLID3_BITS: u32 = 255;
pub const UART_UARTPCELLID3_RESET: u32 = 177;
pub const UART_UARTPCELLID3_UARTPCELLID3_RESET: u32 = 177;
pub const UART_UARTPCELLID3_UARTPCELLID3_BITS: u32 = 255;
pub const UART_UARTPCELLID3_UARTPCELLID3_MSB: u32 = 7;
pub const UART_UARTPCELLID3_UARTPCELLID3_LSB: u32 = 0;
pub const UART_UARTPCELLID3_UARTPCELLID3_ACCESS: &'static [u8; 3usize] = b"RO\0";
pub const PARAM_ASSERTIONS_ENABLED_UART: u32 = 0;
pub const PICO_UART_ENABLE_CRLF_SUPPORT: u32 = 1;
pub const PICO_UART_DEFAULT_CRLF: u32 = 0;
pub const PICO_DEFAULT_UART_BAUD_RATE: u32 = 115200;
pub type int_least8_t = i8;
pub type int_least16_t = i16;
pub type int_least32_t = i32;
pub type int_least64_t = i64;
pub type uint_least8_t = u8;
pub type uint_least16_t = u16;
pub type uint_least32_t = u32;
pub type uint_least64_t = u64;
pub type int_fast8_t = i8;
pub type int_fast16_t = i16;
pub type int_fast32_t = i32;
pub type int_fast64_t = i64;
pub type uint_fast8_t = u8;
pub type uint_fast16_t = u16;
pub type uint_fast32_t = u32;
pub type uint_fast64_t = u64;
pub type __int8_t = crate::ctypes::c_schar;
pub type __uint8_t = crate::ctypes::c_uchar;
pub type __int16_t = crate::ctypes::c_short;
pub type __uint16_t = crate::ctypes::c_ushort;
pub type __int32_t = crate::ctypes::c_int;
pub type __uint32_t = crate::ctypes::c_uint;
pub type __int64_t = crate::ctypes::c_longlong;
pub type __uint64_t = crate::ctypes::c_ulonglong;
pub type __darwin_intptr_t = crate::ctypes::c_long;
pub type __darwin_natural_t = crate::ctypes::c_uint;
pub type __darwin_ct_rune_t = crate::ctypes::c_int;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __mbstate_t {
pub __mbstate8: __BindgenUnionField<[crate::ctypes::c_char; 128usize]>,
pub _mbstateL: __BindgenUnionField<crate::ctypes::c_longlong>,
pub bindgen_union_field: [u64; 16usize],
}
#[test]
fn bindgen_test_layout___mbstate_t() {
assert_eq!(
::core::mem::size_of::<__mbstate_t>(),
128usize,
concat!("Size of: ", stringify!(__mbstate_t))
);
assert_eq!(
::core::mem::align_of::<__mbstate_t>(),
8usize,
concat!("Alignment of ", stringify!(__mbstate_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<__mbstate_t>())).__mbstate8 as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(__mbstate_t),
"::",
stringify!(__mbstate8)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<__mbstate_t>()))._mbstateL as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(__mbstate_t),
"::",
stringify!(_mbstateL)
)
);
}
pub type __darwin_mbstate_t = __mbstate_t;
pub type __darwin_ptrdiff_t = crate::ctypes::c_long;
pub type __darwin_size_t = crate::ctypes::c_ulong;
pub type __darwin_va_list = __builtin_va_list;
pub type __darwin_wchar_t = crate::ctypes::c_int;
pub type __darwin_rune_t = __darwin_wchar_t;
pub type __darwin_wint_t = crate::ctypes::c_int;
pub type __darwin_clock_t = crate::ctypes::c_ulong;
pub type __darwin_socklen_t = __uint32_t;
pub type __darwin_ssize_t = crate::ctypes::c_long;
pub type __darwin_time_t = crate::ctypes::c_long;
pub type __darwin_blkcnt_t = __int64_t;
pub type __darwin_blksize_t = __int32_t;
pub type __darwin_dev_t = __int32_t;
pub type __darwin_fsblkcnt_t = crate::ctypes::c_uint;
pub type __darwin_fsfilcnt_t = crate::ctypes::c_uint;
pub type __darwin_gid_t = __uint32_t;
pub type __darwin_id_t = __uint32_t;
pub type __darwin_ino64_t = __uint64_t;
pub type __darwin_ino_t = __darwin_ino64_t;
pub type __darwin_mach_port_name_t = __darwin_natural_t;
pub type __darwin_mach_port_t = __darwin_mach_port_name_t;
pub type __darwin_mode_t = __uint16_t;
pub type __darwin_off_t = __int64_t;
pub type __darwin_pid_t = __int32_t;
pub type __darwin_sigset_t = __uint32_t;
pub type __darwin_suseconds_t = __int32_t;
pub type __darwin_uid_t = __uint32_t;
pub type __darwin_useconds_t = __uint32_t;
pub type __darwin_uuid_t = [crate::ctypes::c_uchar; 16usize];
pub type __darwin_uuid_string_t = [crate::ctypes::c_char; 37usize];
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __darwin_pthread_handler_rec {
pub __routine: ::core::option::Option<unsafe extern "C" fn(arg1: *mut crate::ctypes::c_void)>,
pub __arg: *mut crate::ctypes::c_void,
pub __next: *mut __darwin_pthread_handler_rec,
}
#[test]
fn bindgen_test_layout___darwin_pthread_handler_rec() {
assert_eq!(
::core::mem::size_of::<__darwin_pthread_handler_rec>(),
24usize,
concat!("Size of: ", stringify!(__darwin_pthread_handler_rec))
);
assert_eq!(
::core::mem::align_of::<__darwin_pthread_handler_rec>(),
8usize,
concat!("Alignment of ", stringify!(__darwin_pthread_handler_rec))
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<__darwin_pthread_handler_rec>())).__routine as *const _ as usize
},
0usize,
concat!(
"Offset of field: ",
stringify!(__darwin_pthread_handler_rec),
"::",
stringify!(__routine)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<__darwin_pthread_handler_rec>())).__arg as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(__darwin_pthread_handler_rec),
"::",
stringify!(__arg)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<__darwin_pthread_handler_rec>())).__next as *const _ as usize
},
16usize,
concat!(
"Offset of field: ",
stringify!(__darwin_pthread_handler_rec),
"::",
stringify!(__next)
)
);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _opaque_pthread_attr_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 56usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_attr_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_attr_t>(),
64usize,
concat!("Size of: ", stringify!(_opaque_pthread_attr_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_attr_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_attr_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_attr_t>())).__sig as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_attr_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_attr_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_attr_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _opaque_pthread_cond_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 40usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_cond_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_cond_t>(),
48usize,
concat!("Size of: ", stringify!(_opaque_pthread_cond_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_cond_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_cond_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_cond_t>())).__sig as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_cond_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_cond_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_cond_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _opaque_pthread_condattr_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 8usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_condattr_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_condattr_t>(),
16usize,
concat!("Size of: ", stringify!(_opaque_pthread_condattr_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_condattr_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_condattr_t))
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_condattr_t>())).__sig as *const _ as usize
},
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_condattr_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_condattr_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_condattr_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _opaque_pthread_mutex_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 56usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_mutex_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_mutex_t>(),
64usize,
concat!("Size of: ", stringify!(_opaque_pthread_mutex_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_mutex_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_mutex_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_mutex_t>())).__sig as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_mutex_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_mutex_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_mutex_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _opaque_pthread_mutexattr_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 8usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_mutexattr_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_mutexattr_t>(),
16usize,
concat!("Size of: ", stringify!(_opaque_pthread_mutexattr_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_mutexattr_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_mutexattr_t))
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_mutexattr_t>())).__sig as *const _ as usize
},
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_mutexattr_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_mutexattr_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_mutexattr_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _opaque_pthread_once_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 8usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_once_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_once_t>(),
16usize,
concat!("Size of: ", stringify!(_opaque_pthread_once_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_once_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_once_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_once_t>())).__sig as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_once_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_once_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_once_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _opaque_pthread_rwlock_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 192usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_rwlock_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_rwlock_t>(),
200usize,
concat!("Size of: ", stringify!(_opaque_pthread_rwlock_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_rwlock_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_rwlock_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_rwlock_t>())).__sig as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_rwlock_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_rwlock_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_rwlock_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _opaque_pthread_rwlockattr_t {
pub __sig: crate::ctypes::c_long,
pub __opaque: [crate::ctypes::c_char; 16usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_rwlockattr_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_rwlockattr_t>(),
24usize,
concat!("Size of: ", stringify!(_opaque_pthread_rwlockattr_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_rwlockattr_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_rwlockattr_t))
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_rwlockattr_t>())).__sig as *const _ as usize
},
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_rwlockattr_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_rwlockattr_t>())).__opaque as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_rwlockattr_t),
"::",
stringify!(__opaque)
)
);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _opaque_pthread_t {
pub __sig: crate::ctypes::c_long,
pub __cleanup_stack: *mut __darwin_pthread_handler_rec,
pub __opaque: [crate::ctypes::c_char; 8176usize],
}
#[test]
fn bindgen_test_layout__opaque_pthread_t() {
assert_eq!(
::core::mem::size_of::<_opaque_pthread_t>(),
8192usize,
concat!("Size of: ", stringify!(_opaque_pthread_t))
);
assert_eq!(
::core::mem::align_of::<_opaque_pthread_t>(),
8usize,
concat!("Alignment of ", stringify!(_opaque_pthread_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_t>())).__sig as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_t),
"::",
stringify!(__sig)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<_opaque_pthread_t>())).__cleanup_stack as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_t),
"::",
stringify!(__cleanup_stack)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<_opaque_pthread_t>())).__opaque as *const _ as usize },
16usize,
concat!(
"Offset of field: ",
stringify!(_opaque_pthread_t),
"::",
stringify!(__opaque)
)
);
}
pub type __darwin_pthread_attr_t = _opaque_pthread_attr_t;
pub type __darwin_pthread_cond_t = _opaque_pthread_cond_t;
pub type __darwin_pthread_condattr_t = _opaque_pthread_condattr_t;
pub type __darwin_pthread_key_t = crate::ctypes::c_ulong;
pub type __darwin_pthread_mutex_t = _opaque_pthread_mutex_t;
pub type __darwin_pthread_mutexattr_t = _opaque_pthread_mutexattr_t;
pub type __darwin_pthread_once_t = _opaque_pthread_once_t;
pub type __darwin_pthread_rwlock_t = _opaque_pthread_rwlock_t;
pub type __darwin_pthread_rwlockattr_t = _opaque_pthread_rwlockattr_t;
pub type __darwin_pthread_t = *mut _opaque_pthread_t;
pub type u_int8_t = crate::ctypes::c_uchar;
pub type u_int16_t = crate::ctypes::c_ushort;
pub type u_int32_t = crate::ctypes::c_uint;
pub type u_int64_t = crate::ctypes::c_ulonglong;
pub type register_t = i64;
pub type user_addr_t = u_int64_t;
pub type user_size_t = u_int64_t;
pub type user_ssize_t = i64;
pub type user_long_t = i64;
pub type user_ulong_t = u_int64_t;
pub type user_time_t = i64;
pub type user_off_t = i64;
pub type syscall_arg_t = u_int64_t;
pub type intmax_t = crate::ctypes::c_long;
pub type uintmax_t = crate::ctypes::c_ulong;
pub type size_t = crate::ctypes::c_ulong;
pub type rsize_t = crate::ctypes::c_ulong;
pub type wchar_t = crate::ctypes::c_int;
pub type max_align_t = u128;
pub type uint = crate::ctypes::c_uint;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct absolute_time_t {
pub _private_us_since_boot: u64,
}
#[test]
fn bindgen_test_layout_absolute_time_t() {
assert_eq!(
::core::mem::size_of::<absolute_time_t>(),
8usize,
concat!("Size of: ", stringify!(absolute_time_t))
);
assert_eq!(
::core::mem::align_of::<absolute_time_t>(),
8usize,
concat!("Alignment of ", stringify!(absolute_time_t))
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<absolute_time_t>()))._private_us_since_boot as *const _ as usize
},
0usize,
concat!(
"Offset of field: ",
stringify!(absolute_time_t),
"::",
stringify!(_private_us_since_boot)
)
);
}
#[doc = " \\struct datetime_t"]
#[doc = " \\ingroup util_datetime"]
#[doc = " \\brief Structure containing date and time information"]
#[doc = ""]
#[doc = " When setting an RTC alarm, set a field to -1 tells"]
#[doc = " the RTC to not match on this field"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct datetime_t {
#[doc = "< 0..4095"]
pub year: i16,
#[doc = "< 1..12, 1 is January"]
pub month: i8,
#[doc = "< 1..28,29,30,31 depending on month"]
pub day: i8,
#[doc = "< 0..6, 0 is Sunday"]
pub dotw: i8,
#[doc = "< 0..23"]
pub hour: i8,
#[doc = "< 0..59"]
pub min: i8,
#[doc = "< 0..59"]
pub sec: i8,
}
#[test]
fn bindgen_test_layout_datetime_t() {
assert_eq!(
::core::mem::size_of::<datetime_t>(),
8usize,
concat!("Size of: ", stringify!(datetime_t))
);
assert_eq!(
::core::mem::align_of::<datetime_t>(),
2usize,
concat!("Alignment of ", stringify!(datetime_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).year as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(year)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).month as *const _ as usize },
2usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(month)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).day as *const _ as usize },
3usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(day)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).dotw as *const _ as usize },
4usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(dotw)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).hour as *const _ as usize },
5usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(hour)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).min as *const _ as usize },
6usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(min)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<datetime_t>())).sec as *const _ as usize },
7usize,
concat!(
"Offset of field: ",
stringify!(datetime_t),
"::",
stringify!(sec)
)
);
}
extern "C" {
pub fn panic_unsupported();
}
extern "C" {
pub fn panic(fmt: *const crate::ctypes::c_char, ...);
}
extern "C" {
pub fn running_on_fpga() -> bool;
}
extern "C" {
pub fn rp2040_chip_version() -> u8;
}
extern "C" {
pub fn __assert_rtn(
arg1: *const crate::ctypes::c_char,
arg2: *const crate::ctypes::c_char,
arg3: crate::ctypes::c_int,
arg4: *const crate::ctypes::c_char,
);
}
pub const PICO_OK: crate::ctypes::c_int = 0;
pub const PICO_ERROR_NONE: crate::ctypes::c_int = 0;
pub const PICO_ERROR_TIMEOUT: crate::ctypes::c_int = -1;
pub const PICO_ERROR_GENERIC: crate::ctypes::c_int = -2;
pub const PICO_ERROR_NO_DATA: crate::ctypes::c_int = -3;
#[doc = " Common return codes from pico_sdk methods that return a status"]
pub type _bindgen_ty_1 = crate::ctypes::c_int;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct stdio_driver {
_unused: [u8; 0],
}
pub type stdio_driver_t = stdio_driver;
extern "C" {
#[doc = " \\brief Initialize all of the present standard stdio types that are linked into the binary."]
#[doc = " \\ingroup pico_stdio"]
#[doc = ""]
#[doc = " Call this method once you have set up your clocks to enable the stdio support for UART, USB"]
#[doc = " and semihosting based on the presence of the respective librariess in the binary."]
#[doc = ""]
#[doc = " \\see stdio_uart, stdio_usb, stdio_semihosting"]
pub fn stdio_init_all();
}
extern "C" {
#[doc = " \\brief Initialize all of the present standard stdio types that are linked into the binary."]
#[doc = " \\ingroup pico_stdio"]
#[doc = ""]
#[doc = " Call this method once you have set up your clocks to enable the stdio support for UART, USB"]
#[doc = " and semihosting based on the presence of the respective librariess in the binary."]
#[doc = ""]
#[doc = " \\see stdio_uart, stdio_usb, stdio_semihosting"]
pub fn stdio_flush();
}
extern "C" {
#[doc = " \\brief Return a character from stdin if there is one available within a timeout"]
#[doc = " \\ingroup pico_stdio"]
#[doc = ""]
#[doc = " \\param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available."]
#[doc = " \\return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs"]
pub fn getchar_timeout_us(timeout_us: u32) -> crate::ctypes::c_int;
}
extern "C" {
#[doc = " \\brief Adds or removes a driver from the list of active drivers used for input/output"]
#[doc = " \\ingroup pico_stdio"]
#[doc = ""]
#[doc = " \\note this method should always be called on an initialized driver"]
#[doc = " \\param driver the driver"]
#[doc = " \\param enabled true to add, false to remove"]
pub fn stdio_set_driver_enabled(driver: *mut stdio_driver_t, enabled: bool);
}
extern "C" {
#[doc = " \\brief Control limiting of output to a single driver"]
#[doc = " \\ingroup pico_stdio"]
#[doc = ""]
#[doc = " \\note this method should always be called on an initialized driver"]
#[doc = ""]
#[doc = " \\param driver if non-null then output only that driver will be used for input/output (assuming it is in the list of enabled drivers)."]
#[doc = " if NULL then all enabled drivers will be used"]
pub fn stdio_filter_driver(driver: *mut stdio_driver_t);
}
extern "C" {
#[doc = " \\brief control conversion of line feeds to carriage return on transmissions"]
#[doc = " \\ingroup pico_stdio"]
#[doc = ""]
#[doc = " \\note this method should always be called on an initialized driver"]
#[doc = ""]
#[doc = " \\param driver the driver"]
#[doc = " \\param translate If true, convert line feeds to carriage return on transmissions"]
pub fn stdio_set_translate_crlf(driver: *mut stdio_driver_t, translate: bool);
}
pub type io_rw_32 = u32;
pub type io_ro_32 = u32;
pub type io_wo_32 = u32;
pub type io_rw_16 = u16;
pub type io_ro_16 = u16;
pub type io_wo_16 = u16;
pub type io_rw_8 = u8;
pub type io_ro_8 = u8;
pub type io_wo_8 = u8;
pub type ioptr = *mut u8;
pub type const_ioptr = ioptr;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct timer_hw_t {
pub timehw: io_wo_32,
pub timelw: io_wo_32,
pub timehr: io_ro_32,
pub timelr: io_ro_32,
pub alarm: [io_rw_32; 4usize],
pub armed: io_rw_32,
pub timerawh: io_ro_32,
pub timerawl: io_ro_32,
pub dbgpause: io_rw_32,
pub pause: io_rw_32,
pub intr: io_rw_32,
pub inte: io_rw_32,
pub intf: io_rw_32,
pub ints: io_ro_32,
}
#[test]
fn bindgen_test_layout_timer_hw_t() {
assert_eq!(
::core::mem::size_of::<timer_hw_t>(),
68usize,
concat!("Size of: ", stringify!(timer_hw_t))
);
assert_eq!(
::core::mem::align_of::<timer_hw_t>(),
4usize,
concat!("Alignment of ", stringify!(timer_hw_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timehw as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(timehw)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timelw as *const _ as usize },
4usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(timelw)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timehr as *const _ as usize },
8usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(timehr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timelr as *const _ as usize },
12usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(timelr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).alarm as *const _ as usize },
16usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(alarm)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).armed as *const _ as usize },
32usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(armed)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timerawh as *const _ as usize },
36usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(timerawh)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timerawl as *const _ as usize },
40usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(timerawl)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).dbgpause as *const _ as usize },
44usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(dbgpause)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).pause as *const _ as usize },
48usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(pause)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).intr as *const _ as usize },
52usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(intr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).inte as *const _ as usize },
56usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(inte)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).intf as *const _ as usize },
60usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(intf)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<timer_hw_t>())).ints as *const _ as usize },
64usize,
concat!(
"Offset of field: ",
stringify!(timer_hw_t),
"::",
stringify!(ints)
)
);
}
extern "C" {
#[doc = " \\brief Return the current 64 bit timestamp value in microseconds"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " Returns the full 64 bits of the hardware timer. The \\ref pico_time and other functions rely on the fact that this"]
#[doc = " value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps"]
#[doc = " (we apologize for introducing a potential year 5851444 bug)."]
#[doc = ""]
#[doc = " \\return the 64 bit timestamp"]
pub fn time_us_64() -> u64;
}
extern "C" {
#[doc = " \\brief Busy wait wasting cycles for the given (32 bit) number of microseconds"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " \\param delay_us delay amount"]
pub fn busy_wait_us_32(delay_us: u32);
}
extern "C" {
#[doc = " \\brief Busy wait wasting cycles for the given (64 bit) number of microseconds"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " \\param delay_us delay amount"]
pub fn busy_wait_us(delay_us: u64);
}
extern "C" {
#[doc = " \\brief Busy wait wasting cycles until after the specified timestamp"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " \\param t Absolute time to wait until"]
pub fn busy_wait_until(t: absolute_time_t);
}
#[doc = " Callback function type for hardware alarms"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " \\param alarm_num the hardware alarm number"]
#[doc = " \\sa hardware_alarm_set_callback"]
pub type hardware_alarm_callback_t = ::core::option::Option<unsafe extern "C" fn(alarm_num: uint)>;
extern "C" {
#[doc = " \\brief cooperatively claim the use of this hardware alarm_num"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " This method hard asserts if the hardware alarm is currently claimed."]
#[doc = ""]
#[doc = " \\param alarm_num the hardware alarm to claim"]
#[doc = " \\sa hardware_claiming"]
pub fn hardware_alarm_claim(alarm_num: uint);
}
extern "C" {
#[doc = " \\brief cooperatively release the claim on use of this hardware alarm_num"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " \\param alarm_num the hardware alarm to unclaim"]
#[doc = " \\sa hardware_claiming"]
pub fn hardware_alarm_unclaim(alarm_num: uint);
}
extern "C" {
#[doc = " \\brief Enable/Disable a callback for a hardware timer on this core"]
#[doc = " \\ingroup hardware_timer"]
#[doc = ""]
#[doc = " This method enables/disables the alarm IRQ for the specified hardware alarm on the"]
#[doc = " calling core, and set the specified callback to be associated with that alarm."]
#[doc = ""]
#[doc = " This callback will be used for the timeout set via hardware_alarm_set_target"]
#[doc = ""]
#[doc = " \\note This will install the handler on the current core if the IRQ handler isn't already set."]
#[doc = " Therefore the user has the opportunity to call this up from the core of their choice"]
#[doc = ""]
#[doc = " \\param alarm_num the hardware alarm number"]
#[doc = " \\param callback the callback to install, or NULL to unset"]
#[doc = ""]
#[doc = " \\sa hardware_alarm_set_target"]
pub fn hardware_alarm_set_callback(alarm_num: uint, callback: hardware_alarm_callback_t);
}
extern "C" {
#[doc = " \\brief Set the current target for the specified hardware alarm"]
#[doc = ""]
#[doc = " This will replace any existing target"]
#[doc = ""]
#[doc = " @param alarm_num the hardware alarm number"]
#[doc = " @param t the target timestamp"]
#[doc = " @return true if the target was \"missed\"; i.e. it was in the past, or occurred before a future hardware timeout could be set"]
pub fn hardware_alarm_set_target(alarm_num: uint, t: absolute_time_t) -> bool;
}
extern "C" {
#[doc = " \\brief Cancel an existing target (if any) for a given hardware_alarm"]
#[doc = ""]
#[doc = " @param alarm_num"]
pub fn hardware_alarm_cancel(alarm_num: uint);
}
extern "C" {
pub static at_the_end_of_time: absolute_time_t;
}
extern "C" {
pub static nil_time: absolute_time_t;
}
extern "C" {
#[doc = " \\brief Wait until after the given timestamp to return"]
#[doc = " \\ingroup sleep"]
#[doc = ""]
#[doc = " \\note This method attempts to perform a lower power (WFE) sleep"]
#[doc = ""]
#[doc = " \\param target the time after which to return"]
#[doc = " \\sa sleep_us()"]
#[doc = " \\sa busy_wait_until()"]
pub fn sleep_until(target: absolute_time_t);
}
extern "C" {
#[doc = " \\brief Wait for the given number of microseconds before returning"]
#[doc = " \\ingroup sleep"]
#[doc = ""]
#[doc = " \\note This method attempts to perform a lower power (WFE) sleep"]
#[doc = ""]
#[doc = " \\param us the number of microseconds to sleep"]
#[doc = " \\sa busy_wait_us()"]
pub fn sleep_us(us: u64);
}
extern "C" {
#[doc = " \\brief Wait for the given number of milliseconds before returning"]
#[doc = " \\ingroup sleep"]
#[doc = ""]
#[doc = " \\note This method attempts to perform a lower power sleep (using WFE) as much as possible."]
#[doc = ""]
#[doc = " \\param ms the number of milliseconds to sleep"]
pub fn sleep_ms(ms: u32);
}
extern "C" {
#[doc = " \\brief Helper method for blocking on a timeout"]
#[doc = " \\ingroup sleep"]
#[doc = ""]
#[doc = " This method will return in response to a an event (as per __wfe) or"]
#[doc = " when the target time is reached, or at any point before."]
#[doc = ""]
#[doc = " This method can be used to implement a lower power polling loop waiting on"]
#[doc = " some condition signalled by an event (__sev())."]
#[doc = ""]
#[doc = " This is called \\a best_effort because under certain circumstances (notably the default timer pool"]
#[doc = " being disabled or full) the best effort is simply to return immediately without a __wfe, thus turning the calling"]
#[doc = " code into a busy wait."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " ```c"]
#[doc = " bool my_function_with_timeout_us(uint64_t timeout_us) {"]
#[doc = " absolute_time_t timeout_time = make_timeout_time_us(timeout_us);"]
#[doc = " do {"]
#[doc = " // each time round the loop, we check to see if the condition"]
#[doc = " // we are waiting on has happened"]
#[doc = " if (my_check_done()) {"]
#[doc = " // do something"]
#[doc = " return true;"]
#[doc = " }"]
#[doc = " // will try to sleep until timeout or the next processor event"]
#[doc = " } while (!best_effort_wfe_or_timeout(timeout_time));"]
#[doc = " return false; // timed out"]
#[doc = " }"]
#[doc = " ```"]
#[doc = ""]
#[doc = " @param timeout_timestamp the timeout time"]
#[doc = " @return true if the target time is reached, false otherwise"]
pub fn best_effort_wfe_or_timeout(timeout_timestamp: absolute_time_t) -> bool;
}
#[doc = " \\brief The identifier for an alarm"]
#[doc = ""]
#[doc = " \\note this identifier is signed because -1 is used as an error condition when creating alarms"]
#[doc = ""]
#[doc = " \\note alarm ids may be reused, however for convenience the implementation makes an attempt to defer"]
#[doc = " reusing as long as possible. You should certainly expect it to be hundreds of ids before one is"]
#[doc = " reused, although in most cases it is more. Nonetheless care must still be taken when cancelling"]
#[doc = " alarms or other functionality based on alarms when the alarm may have expired, as eventually"]
#[doc = " the alarm id may be reused for another alarm."]
#[doc = ""]
#[doc = " \\ingroup alarm"]
pub type alarm_id_t = i32;
#[doc = " \\brief User alarm callback"]
#[doc = " \\ingroup alarm"]
#[doc = " \\param id the alarm_id as returned when the alarm was added"]
#[doc = " \\param user_data the user data passed when the alarm was added"]
#[doc = " \\return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire"]
#[doc = " \\return >0 to reschedule the same alarm this many us from the time this method returns"]
#[doc = " \\return 0 to not reschedule the alarm"]
pub type alarm_callback_t = ::core::option::Option<
unsafe extern "C" fn(id: alarm_id_t, user_data: *mut crate::ctypes::c_void) -> i64,
>;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct alarm_pool {
_unused: [u8; 0],
}
pub type alarm_pool_t = alarm_pool;
extern "C" {
#[doc = " \\brief Create the default alarm pool (if not already created or disabled)"]
#[doc = " \\ingroup alarm"]
pub fn alarm_pool_init_default();
}
extern "C" {
#[doc = " \\brief The default alarm pool used when alarms are added without specifying an alarm pool,"]
#[doc = " and also used by the Pico SDK to support lower power sleeps and timeouts."]
#[doc = ""]
#[doc = " \\ingroup alarm"]
#[doc = " \\sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM"]
pub fn alarm_pool_get_default() -> *mut alarm_pool_t;
}
extern "C" {
#[doc = " \\brief Create an alarm pool"]
#[doc = ""]
#[doc = " The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from."]
#[doc = ""]
#[doc = " In many situations there is never any need for anything other than the default alarm pool, however you"]
#[doc = " might want to create another if you want alarm callbacks on core 1 or require alarm pools of"]
#[doc = " different priority (IRQ priority based preemption of callbacks)"]
#[doc = ""]
#[doc = " \\note This method will hard assert if the hardware alarm is already claimed."]
#[doc = ""]
#[doc = " \\ingroup alarm"]
#[doc = " \\param hardware_alarm_num the hardware alarm to use to back this pool"]
#[doc = " \\param max_timers the maximum number of timers"]
#[doc = " \\note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255"]
#[doc = " \\sa alarm_pool_get_default()"]
#[doc = " \\sa hardware_claiming"]
pub fn alarm_pool_create(hardware_alarm_num: uint, max_timers: uint) -> *mut alarm_pool_t;
}
extern "C" {
#[doc = " \\brief Return the hardware alarm used by an alarm pool"]
#[doc = " \\ingroup alarm"]
#[doc = " \\param pool the pool"]
#[doc = " \\return the hardware alarm used by the pool"]
pub fn alarm_pool_hardware_alarm_num(pool: *mut alarm_pool_t) -> uint;
}
extern "C" {
#[doc = " \\brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm"]
#[doc = " \\ingroup alarm"]
#[doc = " \\param pool the pool"]
#[doc = " \\return the hardware alarm used by the pool"]
pub fn alarm_pool_destroy(pool: *mut alarm_pool_t);
}
extern "C" {
#[doc = " \\brief Add an alarm callback to be called at a specific time"]
#[doc = " \\ingroup alarm"]
#[doc = ""]
#[doc = " Generally the callback is called as soon as possible after the time specified from an IRQ handler"]
#[doc = " on the core the alarm pool was created on. If the callback is in the past or happens before"]
#[doc = " the alarm setup could be completed, then this method will optionally call the callback itself"]
#[doc = " and then return a return code to indicate that the target time has passed."]
#[doc = ""]
#[doc = " \\note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core."]
#[doc = ""]
#[doc = " @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)"]
#[doc = " @param time the timestamp when (after which) the callback should fire"]
#[doc = " @param callback the callback function"]
#[doc = " @param user_data user data to pass to the callback function"]
#[doc = " @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call"]
#[doc = " @return >0 the alarm id"]
#[doc = " @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)"]
#[doc = " @return -1 if there were no alarm slots available"]
pub fn alarm_pool_add_alarm_at(
pool: *mut alarm_pool_t,
time: absolute_time_t,
callback: alarm_callback_t,
user_data: *mut crate::ctypes::c_void,
fire_if_past: bool,
) -> alarm_id_t;
}
extern "C" {
#[doc = " \\brief Cancel an alarm"]
#[doc = " \\ingroup alarm"]
#[doc = " \\param pool the alarm_pool containing the alarm"]
#[doc = " \\param alarm_id the alarm"]
#[doc = " \\return true if the alarm was cancelled, false if it didn't exist"]
#[doc = " \\sa alarm_id_t for a note on reuse of IDs"]
pub fn alarm_pool_cancel_alarm(pool: *mut alarm_pool_t, alarm_id: alarm_id_t) -> bool;
}
#[doc = " \\defgroup repeating_timer repeating_timer"]
#[doc = " \\ingroup pico_time"]
#[doc = " \\brief Repeating Timer functions for simple scheduling of repeated execution"]
#[doc = ""]
#[doc = " \\note The regular \\a alarm_ functionality can be used to make repeating alarms (by return non zero from the callback),"]
#[doc = " however these methods abstract that further (at the cost of a user structure to store the repeat delay in (which"]
#[doc = " the alarm framework does not have space for)."]
pub type repeating_timer_t = repeating_timer;
#[doc = " \\brief Callback for a repeating timer"]
#[doc = " \\ingroup repeating_timer"]
#[doc = " \\param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user"]
#[doc = " \\return true to continue repeating, false to stop."]
pub type repeating_timer_callback_t =
::core::option::Option<unsafe extern "C" fn(rt: *mut repeating_timer_t) -> bool>;
#[doc = " \\brief Information about a repeating timer"]
#[doc = " \\ingroup repeating_timer"]
#[doc = " \\return"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct repeating_timer {
pub delay_us: i64,
pub pool: *mut alarm_pool_t,
pub alarm_id: alarm_id_t,
pub callback: repeating_timer_callback_t,
pub user_data: *mut crate::ctypes::c_void,
}
#[test]
fn bindgen_test_layout_repeating_timer() {
assert_eq!(
::core::mem::size_of::<repeating_timer>(),
40usize,
concat!("Size of: ", stringify!(repeating_timer))
);
assert_eq!(
::core::mem::align_of::<repeating_timer>(),
8usize,
concat!("Alignment of ", stringify!(repeating_timer))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<repeating_timer>())).delay_us as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(repeating_timer),
"::",
stringify!(delay_us)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<repeating_timer>())).pool as *const _ as usize },
8usize,
concat!(
"Offset of field: ",
stringify!(repeating_timer),
"::",
stringify!(pool)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<repeating_timer>())).alarm_id as *const _ as usize },
16usize,
concat!(
"Offset of field: ",
stringify!(repeating_timer),
"::",
stringify!(alarm_id)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<repeating_timer>())).callback as *const _ as usize },
24usize,
concat!(
"Offset of field: ",
stringify!(repeating_timer),
"::",
stringify!(callback)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<repeating_timer>())).user_data as *const _ as usize },
32usize,
concat!(
"Offset of field: ",
stringify!(repeating_timer),
"::",
stringify!(user_data)
)
);
}
extern "C" {
#[doc = " \\brief Add a repeating timer that is called repeatedly at the specified interval in microseconds"]
#[doc = " \\ingroup repeating_timer"]
#[doc = ""]
#[doc = " Generally the callback is called as soon as possible after the time specified from an IRQ handler"]
#[doc = " on the core the alarm pool was created on. If the callback is in the past or happens before"]
#[doc = " the alarm setup could be completed, then this method will optionally call the callback itself"]
#[doc = " and then return a return code to indicate that the target time has passed."]
#[doc = ""]
#[doc = " \\note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core."]
#[doc = ""]
#[doc = " @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback)"]
#[doc = " @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1"]
#[doc = " @param callback the repeating timer callback function"]
#[doc = " @param user_data user data to pass to store in the repeating_timer structure for use by the callback."]
#[doc = " @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space"]
#[doc = " @return false if there were no alarm slots available to create the timer, true otherwise."]
pub fn alarm_pool_add_repeating_timer_us(
pool: *mut alarm_pool_t,
delay_us: i64,
callback: repeating_timer_callback_t,
user_data: *mut crate::ctypes::c_void,
out: *mut repeating_timer_t,
) -> bool;
}
extern "C" {
#[doc = " \\brief Cancel a repeating timer"]
#[doc = " \\ingroup repeating_timer"]
#[doc = " \\param timer the repeating timer to cancel"]
#[doc = " \\return true if the repeating timer was cancelled, false if it didn't exist"]
#[doc = " \\sa alarm_id_t for a note on reuse of IDs"]
pub fn cancel_repeating_timer(timer: *mut repeating_timer_t) -> bool;
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct interp_hw_t {
pub accum: [io_rw_32; 2usize],
pub base: [io_rw_32; 3usize],
pub pop: [io_ro_32; 3usize],
pub peek: [io_ro_32; 3usize],
pub ctrl: [io_rw_32; 2usize],
pub add_raw: [io_rw_32; 2usize],
pub base01: io_wo_32,
}
#[test]
fn bindgen_test_layout_interp_hw_t() {
assert_eq!(
::core::mem::size_of::<interp_hw_t>(),
64usize,
concat!("Size of: ", stringify!(interp_hw_t))
);
assert_eq!(
::core::mem::align_of::<interp_hw_t>(),
4usize,
concat!("Alignment of ", stringify!(interp_hw_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).accum as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(accum)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).base as *const _ as usize },
8usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(base)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).pop as *const _ as usize },
20usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(pop)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).peek as *const _ as usize },
32usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(peek)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).ctrl as *const _ as usize },
44usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(ctrl)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).add_raw as *const _ as usize },
52usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(add_raw)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<interp_hw_t>())).base01 as *const _ as usize },
60usize,
concat!(
"Offset of field: ",
stringify!(interp_hw_t),
"::",
stringify!(base01)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct sio_hw_t {
pub cpuid: io_ro_32,
pub gpio_in: io_ro_32,
pub gpio_hi_in: io_ro_32,
pub _pad: u32,
pub gpio_out: io_wo_32,
pub gpio_set: io_wo_32,
pub gpio_clr: io_wo_32,
pub gpio_togl: io_wo_32,
pub gpio_oe: io_wo_32,
pub gpio_oe_set: io_wo_32,
pub gpio_oe_clr: io_wo_32,
pub gpio_oe_togl: io_wo_32,
pub gpio_hi_out: io_wo_32,
pub gpio_hi_set: io_wo_32,
pub gpio_hi_clr: io_wo_32,
pub gpio_hi_togl: io_wo_32,
pub gpio_hi_oe: io_wo_32,
pub gpio_hi_oe_set: io_wo_32,
pub gpio_hi_oe_clr: io_wo_32,
pub gpio_hi_oe_togl: io_wo_32,
pub fifo_st: io_rw_32,
pub fifo_wr: io_wo_32,
pub fifo_rd: io_ro_32,
pub spinlock_st: io_ro_32,
pub div_udividend: io_rw_32,
pub div_udivisor: io_rw_32,
pub div_sdividend: io_rw_32,
pub div_sdivisor: io_rw_32,
pub div_quotient: io_rw_32,
pub div_remainder: io_rw_32,
pub div_csr: io_rw_32,
pub _pad2: u32,
pub interp: [interp_hw_t; 2usize],
}
#[test]
fn bindgen_test_layout_sio_hw_t() {
assert_eq!(
::core::mem::size_of::<sio_hw_t>(),
256usize,
concat!("Size of: ", stringify!(sio_hw_t))
);
assert_eq!(
::core::mem::align_of::<sio_hw_t>(),
4usize,
concat!("Alignment of ", stringify!(sio_hw_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).cpuid as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(cpuid)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_in as *const _ as usize },
4usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_in)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_in as *const _ as usize },
8usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_in)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>()))._pad as *const _ as usize },
12usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(_pad)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_out as *const _ as usize },
16usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_out)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_set as *const _ as usize },
20usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_set)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_clr as *const _ as usize },
24usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_clr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_togl as *const _ as usize },
28usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_togl)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe as *const _ as usize },
32usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_oe)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe_set as *const _ as usize },
36usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_oe_set)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe_clr as *const _ as usize },
40usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_oe_clr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe_togl as *const _ as usize },
44usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_oe_togl)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_out as *const _ as usize },
48usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_out)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_set as *const _ as usize },
52usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_set)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_clr as *const _ as usize },
56usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_clr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_togl as *const _ as usize },
60usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_togl)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe as *const _ as usize },
64usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_oe)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe_set as *const _ as usize },
68usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_oe_set)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe_clr as *const _ as usize },
72usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_oe_clr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe_togl as *const _ as usize },
76usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(gpio_hi_oe_togl)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).fifo_st as *const _ as usize },
80usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(fifo_st)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).fifo_wr as *const _ as usize },
84usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(fifo_wr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).fifo_rd as *const _ as usize },
88usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(fifo_rd)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).spinlock_st as *const _ as usize },
92usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(spinlock_st)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_udividend as *const _ as usize },
96usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_udividend)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_udivisor as *const _ as usize },
100usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_udivisor)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_sdividend as *const _ as usize },
104usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_sdividend)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_sdivisor as *const _ as usize },
108usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_sdivisor)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_quotient as *const _ as usize },
112usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_quotient)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_remainder as *const _ as usize },
116usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_remainder)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_csr as *const _ as usize },
120usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(div_csr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>()))._pad2 as *const _ as usize },
124usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(_pad2)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<sio_hw_t>())).interp as *const _ as usize },
128usize,
concat!(
"Offset of field: ",
stringify!(sio_hw_t),
"::",
stringify!(interp)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct padsbank0_hw_t {
pub voltage_select: io_rw_32,
pub io: [io_rw_32; 30usize],
}
#[test]
fn bindgen_test_layout_padsbank0_hw_t() {
assert_eq!(
::core::mem::size_of::<padsbank0_hw_t>(),
124usize,
concat!("Size of: ", stringify!(padsbank0_hw_t))
);
assert_eq!(
::core::mem::align_of::<padsbank0_hw_t>(),
4usize,
concat!("Alignment of ", stringify!(padsbank0_hw_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<padsbank0_hw_t>())).voltage_select as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(padsbank0_hw_t),
"::",
stringify!(voltage_select)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<padsbank0_hw_t>())).io as *const _ as usize },
4usize,
concat!(
"Offset of field: ",
stringify!(padsbank0_hw_t),
"::",
stringify!(io)
)
);
}
pub const gpio_function_GPIO_FUNC_XIP: gpio_function = 0;
pub const gpio_function_GPIO_FUNC_SPI: gpio_function = 1;
pub const gpio_function_GPIO_FUNC_UART: gpio_function = 2;
pub const gpio_function_GPIO_FUNC_I2C: gpio_function = 3;
pub const gpio_function_GPIO_FUNC_PWM: gpio_function = 4;
pub const gpio_function_GPIO_FUNC_SIO: gpio_function = 5;
pub const gpio_function_GPIO_FUNC_PIO0: gpio_function = 6;
pub const gpio_function_GPIO_FUNC_PIO1: gpio_function = 7;
pub const gpio_function_GPIO_FUNC_GPCK: gpio_function = 8;
pub const gpio_function_GPIO_FUNC_USB: gpio_function = 9;
pub const gpio_function_GPIO_FUNC_NULL: gpio_function = 15;
#[doc = " \\brief GPIO function definitions for use with function select"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = " \\brief GPIO function selectors"]
#[doc = ""]
#[doc = " Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be"]
#[doc = " selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical"]
#[doc = " OR of these GPIO inputs."]
#[doc = ""]
#[doc = " Please refer to the datsheet for more information on GPIO function selection."]
pub type gpio_function = crate::ctypes::c_uint;
pub const gpio_irq_level_GPIO_IRQ_LEVEL_LOW: gpio_irq_level = 1;
pub const gpio_irq_level_GPIO_IRQ_LEVEL_HIGH: gpio_irq_level = 2;
pub const gpio_irq_level_GPIO_IRQ_EDGE_FALL: gpio_irq_level = 4;
pub const gpio_irq_level_GPIO_IRQ_EDGE_RISE: gpio_irq_level = 8;
#[doc = " \\brief GPIO Interrupt level definitions"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = " \\brief GPIO Interrupt levels"]
#[doc = ""]
#[doc = " An interrupt can be generated for every GPIO pin in 4 scenarios:"]
#[doc = ""]
#[doc = " * Level High: the GPIO pin is a logical 1"]
#[doc = " * Level Low: the GPIO pin is a logical 0"]
#[doc = " * Edge High: the GPIO has transitioned from a logical 0 to a logical 1"]
#[doc = " * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0"]
#[doc = ""]
#[doc = " The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will"]
#[doc = " become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be"]
#[doc = " cleared by writing to the INTR register."]
pub type gpio_irq_level = crate::ctypes::c_uint;
pub type gpio_irq_callback_t =
::core::option::Option<unsafe extern "C" fn(gpio: uint, events: u32)>;
#[doc = "< peripheral signal selected via \\ref gpio_set_function"]
pub const gpio_override_GPIO_OVERRIDE_NORMAL: gpio_override = 0;
#[doc = "< invert peripheral signal selected via \\ref gpio_set_function"]
pub const gpio_override_GPIO_OVERRIDE_INVERT: gpio_override = 1;
#[doc = "< drive low/disable output"]
pub const gpio_override_GPIO_OVERRIDE_LOW: gpio_override = 2;
#[doc = "< drive high/enable output"]
pub const gpio_override_GPIO_OVERRIDE_HIGH: gpio_override = 3;
pub type gpio_override = crate::ctypes::c_uint;
extern "C" {
#[doc = " \\brief Select GPIO function"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param fn Which GPIO function select to use from list \\ref gpio_function"]
pub fn gpio_set_function(gpio: uint, fn_: gpio_function);
}
extern "C" {
pub fn gpio_get_function(gpio: uint) -> gpio_function;
}
extern "C" {
#[doc = " \\brief Select up and down pulls on specific GPIO"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param up If true set a pull up on the GPIO"]
#[doc = " \\param down If true set a pull down on the GPIO"]
#[doc = ""]
#[doc = " \\note On the RP2040, setting both pulls enables a \"bus keep\" function,"]
#[doc = " i.e. a weak pull to whatever is current high/low state of GPIO."]
pub fn gpio_set_pulls(gpio: uint, up: bool, down: bool);
}
extern "C" {
#[doc = " \\brief Set GPIO output override"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param value See \\ref gpio_override"]
pub fn gpio_set_outover(gpio: uint, value: uint);
}
extern "C" {
#[doc = " \\brief Select GPIO input override"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param value See \\ref gpio_override"]
pub fn gpio_set_inover(gpio: uint, value: uint);
}
extern "C" {
#[doc = " \\brief Select GPIO output enable override"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param value See \\ref gpio_override"]
pub fn gpio_set_oeover(gpio: uint, value: uint);
}
extern "C" {
#[doc = " \\brief Enable GPIO input"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param enabled true to enable input on specified GPIO"]
pub fn gpio_set_input_enabled(gpio: uint, enabled: bool);
}
extern "C" {
#[doc = " \\brief Enable or disable interrupts for specified GPIO"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\note The IO IRQs are independent per-processor. This configures IRQs for"]
#[doc = " the processor that calls the function."]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param events Which events will cause an interrupt"]
#[doc = " \\param enabled Enable or disable flag"]
#[doc = ""]
#[doc = " Events is a bitmask of the following:"]
#[doc = ""]
#[doc = " bit | interrupt"]
#[doc = " ----|----------"]
#[doc = " 0 | Low level"]
#[doc = " 1 | High level"]
#[doc = " 2 | Edge low"]
#[doc = " 3 | Edge high"]
pub fn gpio_set_irq_enabled(gpio: uint, events: u32, enabled: bool);
}
extern "C" {
#[doc = " \\brief Enable interrupts for specified GPIO"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\note The IO IRQs are independent per-processor. This configures IRQs for"]
#[doc = " the processor that calls the function."]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param events Which events will cause an interrupt See \\ref gpio_set_irq_enabled for details."]
#[doc = " \\param enabled Enable or disable flag"]
#[doc = " \\param callback user function to call on GPIO irq. Note only one of these can be set per processor."]
#[doc = ""]
#[doc = " \\note Currently the GPIO parameter is ignored, and this callback will be called for any enabled GPIO IRQ on any pin."]
#[doc = ""]
pub fn gpio_set_irq_enabled_with_callback(
gpio: uint,
events: u32,
enabled: bool,
callback: gpio_irq_callback_t,
);
}
extern "C" {
#[doc = " \\brief Enable dormant wake up interrupt for specified GPIO"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " This configures IRQs to restart the XOSC or ROSC when they are"]
#[doc = " disabled in dormant mode"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param events Which events will cause an interrupt. See \\ref gpio_set_irq_enabled for details."]
#[doc = " \\param enabled Enable/disable flag"]
pub fn gpio_set_dormant_irq_enabled(gpio: uint, events: u32, enabled: bool);
}
extern "C" {
#[doc = " \\brief Acknowledge a GPIO interrupt"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
#[doc = " \\param events Bitmask of events to clear. See \\ref gpio_set_irq_enabled for details."]
#[doc = ""]
pub fn gpio_acknowledge_irq(gpio: uint, events: u32);
}
extern "C" {
#[doc = " \\brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " Clear the output enable (i.e. set to input)"]
#[doc = " Clear any output value."]
#[doc = ""]
#[doc = " \\param gpio GPIO number"]
pub fn gpio_init(gpio: uint);
}
extern "C" {
#[doc = " \\brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)"]
#[doc = " \\ingroup hardware_gpio"]
#[doc = ""]
#[doc = " Clear the output enable (i.e. set to input)"]
#[doc = " Clear any output value."]
#[doc = ""]
#[doc = " \\param gpio_mask Mask with 1 bit per GPIO number to initialize"]
pub fn gpio_init_mask(gpio_mask: uint);
}
extern "C" {
pub fn gpio_debug_pins_init();
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct uart_hw_t {
pub dr: io_rw_32,
pub rsr: io_rw_32,
pub _pad0: [u32; 4usize],
pub fr: io_rw_32,
pub _pad1: u32,
pub ilpr: io_rw_32,
pub ibrd: io_rw_32,
pub fbrd: io_rw_32,
pub lcr_h: io_rw_32,
pub cr: io_rw_32,
pub ifls: io_rw_32,
pub imsc: io_rw_32,
pub ris: io_rw_32,
pub mis: io_rw_32,
pub icr: io_rw_32,
pub dmacr: io_rw_32,
}
#[test]
fn bindgen_test_layout_uart_hw_t() {
assert_eq!(
::core::mem::size_of::<uart_hw_t>(),
76usize,
concat!("Size of: ", stringify!(uart_hw_t))
);
assert_eq!(
::core::mem::align_of::<uart_hw_t>(),
4usize,
concat!("Alignment of ", stringify!(uart_hw_t))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).dr as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(dr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).rsr as *const _ as usize },
4usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(rsr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>()))._pad0 as *const _ as usize },
8usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(_pad0)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).fr as *const _ as usize },
24usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(fr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>()))._pad1 as *const _ as usize },
28usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(_pad1)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ilpr as *const _ as usize },
32usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(ilpr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ibrd as *const _ as usize },
36usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(ibrd)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).fbrd as *const _ as usize },
40usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(fbrd)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).lcr_h as *const _ as usize },
44usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(lcr_h)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).cr as *const _ as usize },
48usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(cr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ifls as *const _ as usize },
52usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(ifls)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).imsc as *const _ as usize },
56usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(imsc)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ris as *const _ as usize },
60usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(ris)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).mis as *const _ as usize },
64usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(mis)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).icr as *const _ as usize },
68usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(icr)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<uart_hw_t>())).dmacr as *const _ as usize },
72usize,
concat!(
"Offset of field: ",
stringify!(uart_hw_t),
"::",
stringify!(dmacr)
)
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct uart_inst {
_unused: [u8; 0],
}
#[doc = " \\file hardware/uart.h"]
#[doc = " \\defgroup hardware_uart hardware_uart"]
#[doc = ""]
#[doc = " Hardware UART API"]
#[doc = ""]
#[doc = " RP2040 has 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number"]
#[doc = " of GPIO pins as defined in the GPIO muxing."]
#[doc = ""]
#[doc = " Only the TX, RX, RTS, and CTS signals are"]
#[doc = " connected, meaning that the modem mode and IrDA mode of the PL011 are not supported."]
#[doc = ""]
#[doc = " \\subsection uart_example Example"]
#[doc = " \\addtogroup hardware_uart"]
#[doc = ""]
#[doc = " \\code"]
#[doc = " int main() {"]
#[doc = ""]
#[doc = " // Initialise UART 0"]
#[doc = " uart_init(uart0, 115200);"]
#[doc = ""]
#[doc = " // Set the GPIO pin mux to the UART - 0 is TX, 1 is RX"]
#[doc = " gpio_set_function(0, GPIO_FUNC_UART);"]
#[doc = " gpio_set_function(1, GPIO_FUNC_UART);"]
#[doc = ""]
#[doc = " uart_puts(uart0, \"Hello world!\");"]
#[doc = " }"]
#[doc = " \\endcode"]
pub type uart_inst_t = uart_inst;
pub const uart_parity_t_UART_PARITY_NONE: uart_parity_t = 0;
pub const uart_parity_t_UART_PARITY_EVEN: uart_parity_t = 1;
pub const uart_parity_t_UART_PARITY_ODD: uart_parity_t = 2;
#[doc = " \\brief UART Parity enumeration"]
#[doc = " \\ingroup hardware_uart"]
pub type uart_parity_t = crate::ctypes::c_uint;
extern "C" {
#[doc = " \\brief Initialise a UART"]
#[doc = " \\ingroup hardware_uart"]
#[doc = ""]
#[doc = " Put the UART into a known state, and enable it. Must be called before other"]
#[doc = " functions."]
#[doc = ""]
#[doc = " \\note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen,"]
#[doc = " and this function will return the configured baud rate."]
#[doc = ""]
#[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
#[doc = " \\param baudrate Baudrate of UART in Hz"]
#[doc = " \\return Actual set baudrate"]
pub fn uart_init(uart: *mut uart_inst_t, baudrate: uint) -> uint;
}
extern "C" {
#[doc = " \\brief DeInitialise a UART"]
#[doc = " \\ingroup hardware_uart"]
#[doc = ""]
#[doc = " Disable the UART if it is no longer used. Must be reinitialised before"]
#[doc = " being used again."]
#[doc = ""]
#[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
pub fn uart_deinit(uart: *mut uart_inst_t);
}
extern "C" {
#[doc = " \\brief Set UART baud rate"]
#[doc = " \\ingroup hardware_uart"]
#[doc = ""]
#[doc = " Set baud rate as close as possible to requested, and return actual rate selected."]
#[doc = ""]
#[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
#[doc = " \\param baudrate Baudrate in Hz"]
pub fn uart_set_baudrate(uart: *mut uart_inst_t, baudrate: uint) -> uint;
}
extern "C" {
#[doc = " \\brief Set CR/LF conversion on UART"]
#[doc = " \\ingroup hardware_uart"]
#[doc = ""]
#[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
#[doc = " \\param translate If true, convert line feeds to carriage return on transmissions"]
pub fn uart_set_translate_crlf(uart: *mut uart_inst_t, translate: bool);
}
extern "C" {
#[doc = " \\brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty"]
#[doc = " \\ingroup hardware_uart"]
#[doc = ""]
#[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
#[doc = " \\param us the number of microseconds to wait at most (may be 0 for an instantaneous check)"]
#[doc = " \\return true if the RX FIFO became non empty before the timeout, false otherwise"]
pub fn uart_is_readable_within_us(uart: *mut uart_inst_t, us: u32) -> bool;
}
extern "C" {
#[doc = " \\brief Set up the default UART and assign it to the default GPIO's"]
#[doc = " \\ingroup pico_stdlib"]
#[doc = ""]
#[doc = " By default this will use UART 0, with TX to pin GPIO 0,"]
#[doc = " RX to pin GPIO 1, and the baudrate to 115200"]
#[doc = ""]
#[doc = " Calling this method also initializes stdin/stdout over UART if the"]
#[doc = " @ref pico_stdio_uart library is linked."]
#[doc = ""]
#[doc = " Defaults can be changed using configuration defines,"]
#[doc = " PICO_DEFAULT_UART_INSTANCE,"]
#[doc = " PICO_DEFAULT_UART_BAUD_RATE"]
#[doc = " PICO_DEFAULT_UART_TX_PIN"]
#[doc = " PICO_DEFAULT_UART_RX_PIN"]
pub fn setup_default_uart();
}
extern "C" {
#[doc = " \\brief Initialise the system clock to 48MHz"]
#[doc = " \\ingroup pico_stdlib"]
#[doc = ""]
#[doc = " Set the system clock to 48MHz, and set the peripheral clock to match."]
pub fn set_sys_clock_48mhz();
}
extern "C" {
#[doc = " \\brief Initialise the system clock"]
#[doc = " \\ingroup pico_stdlib"]
#[doc = ""]
#[doc = " \\param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL"]
#[doc = " \\param post_div1 The first post divider for the SYS PLL"]
#[doc = " \\param post_div2 The second post divider for the SYS PLL."]
#[doc = ""]
#[doc = " See the PLL documentation in the datasheet for details of driving the PLLs."]
pub fn set_sys_clock_pll(vco_freq: u32, post_div1: uint, post_div2: uint);
}
extern "C" {
#[doc = " \\brief Check if a given system clock frequency is valid/attainable"]
#[doc = " \\ingroup pico_stdlib"]
#[doc = ""]
#[doc = " \\param freq_khz Requested frequency"]
#[doc = " \\param vco_freq_out On success, the voltage controller oscillator frequeucny to be used by the SYS PLL"]
#[doc = " \\param post_div1_out On success, The first post divider for the SYS PLL"]
#[doc = " \\param post_div2_out On success, The second post divider for the SYS PLL."]
#[doc = " @return true if the frequency is possible and the output parameters have been written."]
pub fn check_sys_clock_khz(
freq_khz: u32,
vco_freq_out: *mut uint,
post_div1_out: *mut uint,
post_div2_out: *mut uint,
) -> bool;
}
pub type __builtin_va_list = [__va_list_tag; 1usize];
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __va_list_tag {
pub gp_offset: crate::ctypes::c_uint,
pub fp_offset: crate::ctypes::c_uint,
pub overflow_arg_area: *mut crate::ctypes::c_void,
pub reg_save_area: *mut crate::ctypes::c_void,
}
#[test]
fn bindgen_test_layout___va_list_tag() {
assert_eq!(
::core::mem::size_of::<__va_list_tag>(),
24usize,
concat!("Size of: ", stringify!(__va_list_tag))
);
assert_eq!(
::core::mem::align_of::<__va_list_tag>(),
8usize,
concat!("Alignment of ", stringify!(__va_list_tag))
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<__va_list_tag>())).gp_offset as *const _ as usize },
0usize,
concat!(
"Offset of field: ",
stringify!(__va_list_tag),
"::",
stringify!(gp_offset)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<__va_list_tag>())).fp_offset as *const _ as usize },
4usize,
concat!(
"Offset of field: ",
stringify!(__va_list_tag),
"::",
stringify!(fp_offset)
)
);
assert_eq!(
unsafe {
&(*(::core::ptr::null::<__va_list_tag>())).overflow_arg_area as *const _ as usize
},
8usize,
concat!(
"Offset of field: ",
stringify!(__va_list_tag),
"::",
stringify!(overflow_arg_area)
)
);
assert_eq!(
unsafe { &(*(::core::ptr::null::<__va_list_tag>())).reg_save_area as *const _ as usize },
16usize,
concat!(
"Offset of field: ",
stringify!(__va_list_tag),
"::",
stringify!(reg_save_area)
)
);
}