1#[doc = "Reader of register CH6_CTRL_TRIG"]
2pub type R = crate::R<u32, super::CH6_CTRL_TRIG>;
3#[doc = "Writer for register CH6_CTRL_TRIG"]
4pub type W = crate::W<u32, super::CH6_CTRL_TRIG>;
5#[doc = "Register CH6_CTRL_TRIG `reset()`'s with value 0x3000"]
6impl crate::ResetValue for super::CH6_CTRL_TRIG {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x3000
11 }
12}
13#[doc = "Reader of field `AHB_ERROR`"]
14pub type AHB_ERROR_R = crate::R<bool, bool>;
15#[doc = "Reader of field `READ_ERROR`"]
16pub type READ_ERROR_R = crate::R<bool, bool>;
17#[doc = "Write proxy for field `READ_ERROR`"]
18pub struct READ_ERROR_W<'a> {
19 w: &'a mut W,
20}
21impl<'a> READ_ERROR_W<'a> {
22 #[doc = r"Sets the field bit"]
23 #[inline(always)]
24 pub fn set_bit(self) -> &'a mut W {
25 self.bit(true)
26 }
27 #[doc = r"Clears the field bit"]
28 #[inline(always)]
29 pub fn clear_bit(self) -> &'a mut W {
30 self.bit(false)
31 }
32 #[doc = r"Writes raw bits to the field"]
33 #[inline(always)]
34 pub fn bit(self, value: bool) -> &'a mut W {
35 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
36 self.w
37 }
38}
39#[doc = "Reader of field `WRITE_ERROR`"]
40pub type WRITE_ERROR_R = crate::R<bool, bool>;
41#[doc = "Write proxy for field `WRITE_ERROR`"]
42pub struct WRITE_ERROR_W<'a> {
43 w: &'a mut W,
44}
45impl<'a> WRITE_ERROR_W<'a> {
46 #[doc = r"Sets the field bit"]
47 #[inline(always)]
48 pub fn set_bit(self) -> &'a mut W {
49 self.bit(true)
50 }
51 #[doc = r"Clears the field bit"]
52 #[inline(always)]
53 pub fn clear_bit(self) -> &'a mut W {
54 self.bit(false)
55 }
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub fn bit(self, value: bool) -> &'a mut W {
59 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
60 self.w
61 }
62}
63#[doc = "Reader of field `BUSY`"]
64pub type BUSY_R = crate::R<bool, bool>;
65#[doc = "Reader of field `SNIFF_EN`"]
66pub type SNIFF_EN_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `SNIFF_EN`"]
68pub struct SNIFF_EN_W<'a> {
69 w: &'a mut W,
70}
71impl<'a> SNIFF_EN_W<'a> {
72 #[doc = r"Sets the field bit"]
73 #[inline(always)]
74 pub fn set_bit(self) -> &'a mut W {
75 self.bit(true)
76 }
77 #[doc = r"Clears the field bit"]
78 #[inline(always)]
79 pub fn clear_bit(self) -> &'a mut W {
80 self.bit(false)
81 }
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub fn bit(self, value: bool) -> &'a mut W {
85 self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
86 self.w
87 }
88}
89#[doc = "Reader of field `BSWAP`"]
90pub type BSWAP_R = crate::R<bool, bool>;
91#[doc = "Write proxy for field `BSWAP`"]
92pub struct BSWAP_W<'a> {
93 w: &'a mut W,
94}
95impl<'a> BSWAP_W<'a> {
96 #[doc = r"Sets the field bit"]
97 #[inline(always)]
98 pub fn set_bit(self) -> &'a mut W {
99 self.bit(true)
100 }
101 #[doc = r"Clears the field bit"]
102 #[inline(always)]
103 pub fn clear_bit(self) -> &'a mut W {
104 self.bit(false)
105 }
106 #[doc = r"Writes raw bits to the field"]
107 #[inline(always)]
108 pub fn bit(self, value: bool) -> &'a mut W {
109 self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
110 self.w
111 }
112}
113#[doc = "Reader of field `IRQ_QUIET`"]
114pub type IRQ_QUIET_R = crate::R<bool, bool>;
115#[doc = "Write proxy for field `IRQ_QUIET`"]
116pub struct IRQ_QUIET_W<'a> {
117 w: &'a mut W,
118}
119impl<'a> IRQ_QUIET_W<'a> {
120 #[doc = r"Sets the field bit"]
121 #[inline(always)]
122 pub fn set_bit(self) -> &'a mut W {
123 self.bit(true)
124 }
125 #[doc = r"Clears the field bit"]
126 #[inline(always)]
127 pub fn clear_bit(self) -> &'a mut W {
128 self.bit(false)
129 }
130 #[doc = r"Writes raw bits to the field"]
131 #[inline(always)]
132 pub fn bit(self, value: bool) -> &'a mut W {
133 self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
134 self.w
135 }
136}
137#[doc = "Select a Transfer Request signal.\\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n 0x0 to 0x3a -> select DREQ n as TREQ\n\nValue on reset: 0"]
138#[derive(Clone, Copy, Debug, PartialEq)]
139#[repr(u8)]
140pub enum TREQ_SEL_A {
141 #[doc = "59: Select Timer 0 as TREQ"]
142 TIMER0 = 59,
143 #[doc = "60: Select Timer 1 as TREQ"]
144 TIMER1 = 60,
145 #[doc = "61: Select Timer 2 as TREQ (Optional)"]
146 TIMER2 = 61,
147 #[doc = "62: Select Timer 3 as TREQ (Optional)"]
148 TIMER3 = 62,
149 #[doc = "63: Permanent request, for unpaced transfers."]
150 PERMANENT = 63,
151}
152impl From<TREQ_SEL_A> for u8 {
153 #[inline(always)]
154 fn from(variant: TREQ_SEL_A) -> Self {
155 variant as _
156 }
157}
158#[doc = "Reader of field `TREQ_SEL`"]
159pub type TREQ_SEL_R = crate::R<u8, TREQ_SEL_A>;
160impl TREQ_SEL_R {
161 #[doc = r"Get enumerated values variant"]
162 #[inline(always)]
163 pub fn variant(&self) -> crate::Variant<u8, TREQ_SEL_A> {
164 use crate::Variant::*;
165 match self.bits {
166 59 => Val(TREQ_SEL_A::TIMER0),
167 60 => Val(TREQ_SEL_A::TIMER1),
168 61 => Val(TREQ_SEL_A::TIMER2),
169 62 => Val(TREQ_SEL_A::TIMER3),
170 63 => Val(TREQ_SEL_A::PERMANENT),
171 i => Res(i),
172 }
173 }
174 #[doc = "Checks if the value of the field is `TIMER0`"]
175 #[inline(always)]
176 pub fn is_timer0(&self) -> bool {
177 *self == TREQ_SEL_A::TIMER0
178 }
179 #[doc = "Checks if the value of the field is `TIMER1`"]
180 #[inline(always)]
181 pub fn is_timer1(&self) -> bool {
182 *self == TREQ_SEL_A::TIMER1
183 }
184 #[doc = "Checks if the value of the field is `TIMER2`"]
185 #[inline(always)]
186 pub fn is_timer2(&self) -> bool {
187 *self == TREQ_SEL_A::TIMER2
188 }
189 #[doc = "Checks if the value of the field is `TIMER3`"]
190 #[inline(always)]
191 pub fn is_timer3(&self) -> bool {
192 *self == TREQ_SEL_A::TIMER3
193 }
194 #[doc = "Checks if the value of the field is `PERMANENT`"]
195 #[inline(always)]
196 pub fn is_permanent(&self) -> bool {
197 *self == TREQ_SEL_A::PERMANENT
198 }
199}
200#[doc = "Write proxy for field `TREQ_SEL`"]
201pub struct TREQ_SEL_W<'a> {
202 w: &'a mut W,
203}
204impl<'a> TREQ_SEL_W<'a> {
205 #[doc = r"Writes `variant` to the field"]
206 #[inline(always)]
207 pub fn variant(self, variant: TREQ_SEL_A) -> &'a mut W {
208 unsafe { self.bits(variant.into()) }
209 }
210 #[doc = "Select Timer 0 as TREQ"]
211 #[inline(always)]
212 pub fn timer0(self) -> &'a mut W {
213 self.variant(TREQ_SEL_A::TIMER0)
214 }
215 #[doc = "Select Timer 1 as TREQ"]
216 #[inline(always)]
217 pub fn timer1(self) -> &'a mut W {
218 self.variant(TREQ_SEL_A::TIMER1)
219 }
220 #[doc = "Select Timer 2 as TREQ (Optional)"]
221 #[inline(always)]
222 pub fn timer2(self) -> &'a mut W {
223 self.variant(TREQ_SEL_A::TIMER2)
224 }
225 #[doc = "Select Timer 3 as TREQ (Optional)"]
226 #[inline(always)]
227 pub fn timer3(self) -> &'a mut W {
228 self.variant(TREQ_SEL_A::TIMER3)
229 }
230 #[doc = "Permanent request, for unpaced transfers."]
231 #[inline(always)]
232 pub fn permanent(self) -> &'a mut W {
233 self.variant(TREQ_SEL_A::PERMANENT)
234 }
235 #[doc = r"Writes raw bits to the field"]
236 #[inline(always)]
237 pub unsafe fn bits(self, value: u8) -> &'a mut W {
238 self.w.bits = (self.w.bits & !(0x3f << 15)) | (((value as u32) & 0x3f) << 15);
239 self.w
240 }
241}
242#[doc = "Reader of field `CHAIN_TO`"]
243pub type CHAIN_TO_R = crate::R<u8, u8>;
244#[doc = "Write proxy for field `CHAIN_TO`"]
245pub struct CHAIN_TO_W<'a> {
246 w: &'a mut W,
247}
248impl<'a> CHAIN_TO_W<'a> {
249 #[doc = r"Writes raw bits to the field"]
250 #[inline(always)]
251 pub unsafe fn bits(self, value: u8) -> &'a mut W {
252 self.w.bits = (self.w.bits & !(0x0f << 11)) | (((value as u32) & 0x0f) << 11);
253 self.w
254 }
255}
256#[doc = "Reader of field `RING_SEL`"]
257pub type RING_SEL_R = crate::R<bool, bool>;
258#[doc = "Write proxy for field `RING_SEL`"]
259pub struct RING_SEL_W<'a> {
260 w: &'a mut W,
261}
262impl<'a> RING_SEL_W<'a> {
263 #[doc = r"Sets the field bit"]
264 #[inline(always)]
265 pub fn set_bit(self) -> &'a mut W {
266 self.bit(true)
267 }
268 #[doc = r"Clears the field bit"]
269 #[inline(always)]
270 pub fn clear_bit(self) -> &'a mut W {
271 self.bit(false)
272 }
273 #[doc = r"Writes raw bits to the field"]
274 #[inline(always)]
275 pub fn bit(self, value: bool) -> &'a mut W {
276 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
277 self.w
278 }
279}
280#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.\n\nValue on reset: 0"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282#[repr(u8)]
283pub enum RING_SIZE_A {
284 #[doc = "0: `0`"]
285 RING_NONE = 0,
286}
287impl From<RING_SIZE_A> for u8 {
288 #[inline(always)]
289 fn from(variant: RING_SIZE_A) -> Self {
290 variant as _
291 }
292}
293#[doc = "Reader of field `RING_SIZE`"]
294pub type RING_SIZE_R = crate::R<u8, RING_SIZE_A>;
295impl RING_SIZE_R {
296 #[doc = r"Get enumerated values variant"]
297 #[inline(always)]
298 pub fn variant(&self) -> crate::Variant<u8, RING_SIZE_A> {
299 use crate::Variant::*;
300 match self.bits {
301 0 => Val(RING_SIZE_A::RING_NONE),
302 i => Res(i),
303 }
304 }
305 #[doc = "Checks if the value of the field is `RING_NONE`"]
306 #[inline(always)]
307 pub fn is_ring_none(&self) -> bool {
308 *self == RING_SIZE_A::RING_NONE
309 }
310}
311#[doc = "Write proxy for field `RING_SIZE`"]
312pub struct RING_SIZE_W<'a> {
313 w: &'a mut W,
314}
315impl<'a> RING_SIZE_W<'a> {
316 #[doc = r"Writes `variant` to the field"]
317 #[inline(always)]
318 pub fn variant(self, variant: RING_SIZE_A) -> &'a mut W {
319 unsafe { self.bits(variant.into()) }
320 }
321 #[doc = "`0`"]
322 #[inline(always)]
323 pub fn ring_none(self) -> &'a mut W {
324 self.variant(RING_SIZE_A::RING_NONE)
325 }
326 #[doc = r"Writes raw bits to the field"]
327 #[inline(always)]
328 pub unsafe fn bits(self, value: u8) -> &'a mut W {
329 self.w.bits = (self.w.bits & !(0x0f << 6)) | (((value as u32) & 0x0f) << 6);
330 self.w
331 }
332}
333#[doc = "Reader of field `INCR_WRITE`"]
334pub type INCR_WRITE_R = crate::R<bool, bool>;
335#[doc = "Write proxy for field `INCR_WRITE`"]
336pub struct INCR_WRITE_W<'a> {
337 w: &'a mut W,
338}
339impl<'a> INCR_WRITE_W<'a> {
340 #[doc = r"Sets the field bit"]
341 #[inline(always)]
342 pub fn set_bit(self) -> &'a mut W {
343 self.bit(true)
344 }
345 #[doc = r"Clears the field bit"]
346 #[inline(always)]
347 pub fn clear_bit(self) -> &'a mut W {
348 self.bit(false)
349 }
350 #[doc = r"Writes raw bits to the field"]
351 #[inline(always)]
352 pub fn bit(self, value: bool) -> &'a mut W {
353 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
354 self.w
355 }
356}
357#[doc = "Reader of field `INCR_READ`"]
358pub type INCR_READ_R = crate::R<bool, bool>;
359#[doc = "Write proxy for field `INCR_READ`"]
360pub struct INCR_READ_W<'a> {
361 w: &'a mut W,
362}
363impl<'a> INCR_READ_W<'a> {
364 #[doc = r"Sets the field bit"]
365 #[inline(always)]
366 pub fn set_bit(self) -> &'a mut W {
367 self.bit(true)
368 }
369 #[doc = r"Clears the field bit"]
370 #[inline(always)]
371 pub fn clear_bit(self) -> &'a mut W {
372 self.bit(false)
373 }
374 #[doc = r"Writes raw bits to the field"]
375 #[inline(always)]
376 pub fn bit(self, value: bool) -> &'a mut W {
377 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
378 self.w
379 }
380}
381#[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.\n\nValue on reset: 0"]
382#[derive(Clone, Copy, Debug, PartialEq)]
383#[repr(u8)]
384pub enum DATA_SIZE_A {
385 #[doc = "0: `0`"]
386 SIZE_BYTE = 0,
387 #[doc = "1: `1`"]
388 SIZE_HALFWORD = 1,
389 #[doc = "2: `10`"]
390 SIZE_WORD = 2,
391}
392impl From<DATA_SIZE_A> for u8 {
393 #[inline(always)]
394 fn from(variant: DATA_SIZE_A) -> Self {
395 variant as _
396 }
397}
398#[doc = "Reader of field `DATA_SIZE`"]
399pub type DATA_SIZE_R = crate::R<u8, DATA_SIZE_A>;
400impl DATA_SIZE_R {
401 #[doc = r"Get enumerated values variant"]
402 #[inline(always)]
403 pub fn variant(&self) -> crate::Variant<u8, DATA_SIZE_A> {
404 use crate::Variant::*;
405 match self.bits {
406 0 => Val(DATA_SIZE_A::SIZE_BYTE),
407 1 => Val(DATA_SIZE_A::SIZE_HALFWORD),
408 2 => Val(DATA_SIZE_A::SIZE_WORD),
409 i => Res(i),
410 }
411 }
412 #[doc = "Checks if the value of the field is `SIZE_BYTE`"]
413 #[inline(always)]
414 pub fn is_size_byte(&self) -> bool {
415 *self == DATA_SIZE_A::SIZE_BYTE
416 }
417 #[doc = "Checks if the value of the field is `SIZE_HALFWORD`"]
418 #[inline(always)]
419 pub fn is_size_halfword(&self) -> bool {
420 *self == DATA_SIZE_A::SIZE_HALFWORD
421 }
422 #[doc = "Checks if the value of the field is `SIZE_WORD`"]
423 #[inline(always)]
424 pub fn is_size_word(&self) -> bool {
425 *self == DATA_SIZE_A::SIZE_WORD
426 }
427}
428#[doc = "Write proxy for field `DATA_SIZE`"]
429pub struct DATA_SIZE_W<'a> {
430 w: &'a mut W,
431}
432impl<'a> DATA_SIZE_W<'a> {
433 #[doc = r"Writes `variant` to the field"]
434 #[inline(always)]
435 pub fn variant(self, variant: DATA_SIZE_A) -> &'a mut W {
436 unsafe { self.bits(variant.into()) }
437 }
438 #[doc = "`0`"]
439 #[inline(always)]
440 pub fn size_byte(self) -> &'a mut W {
441 self.variant(DATA_SIZE_A::SIZE_BYTE)
442 }
443 #[doc = "`1`"]
444 #[inline(always)]
445 pub fn size_halfword(self) -> &'a mut W {
446 self.variant(DATA_SIZE_A::SIZE_HALFWORD)
447 }
448 #[doc = "`10`"]
449 #[inline(always)]
450 pub fn size_word(self) -> &'a mut W {
451 self.variant(DATA_SIZE_A::SIZE_WORD)
452 }
453 #[doc = r"Writes raw bits to the field"]
454 #[inline(always)]
455 pub unsafe fn bits(self, value: u8) -> &'a mut W {
456 self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
457 self.w
458 }
459}
460#[doc = "Reader of field `HIGH_PRIORITY`"]
461pub type HIGH_PRIORITY_R = crate::R<bool, bool>;
462#[doc = "Write proxy for field `HIGH_PRIORITY`"]
463pub struct HIGH_PRIORITY_W<'a> {
464 w: &'a mut W,
465}
466impl<'a> HIGH_PRIORITY_W<'a> {
467 #[doc = r"Sets the field bit"]
468 #[inline(always)]
469 pub fn set_bit(self) -> &'a mut W {
470 self.bit(true)
471 }
472 #[doc = r"Clears the field bit"]
473 #[inline(always)]
474 pub fn clear_bit(self) -> &'a mut W {
475 self.bit(false)
476 }
477 #[doc = r"Writes raw bits to the field"]
478 #[inline(always)]
479 pub fn bit(self, value: bool) -> &'a mut W {
480 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
481 self.w
482 }
483}
484#[doc = "Reader of field `EN`"]
485pub type EN_R = crate::R<bool, bool>;
486#[doc = "Write proxy for field `EN`"]
487pub struct EN_W<'a> {
488 w: &'a mut W,
489}
490impl<'a> EN_W<'a> {
491 #[doc = r"Sets the field bit"]
492 #[inline(always)]
493 pub fn set_bit(self) -> &'a mut W {
494 self.bit(true)
495 }
496 #[doc = r"Clears the field bit"]
497 #[inline(always)]
498 pub fn clear_bit(self) -> &'a mut W {
499 self.bit(false)
500 }
501 #[doc = r"Writes raw bits to the field"]
502 #[inline(always)]
503 pub fn bit(self, value: bool) -> &'a mut W {
504 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
505 self.w
506 }
507}
508impl R {
509 #[doc = "Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."]
510 #[inline(always)]
511 pub fn ahb_error(&self) -> AHB_ERROR_R {
512 AHB_ERROR_R::new(((self.bits >> 31) & 0x01) != 0)
513 }
514 #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear.\\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"]
515 #[inline(always)]
516 pub fn read_error(&self) -> READ_ERROR_R {
517 READ_ERROR_R::new(((self.bits >> 30) & 0x01) != 0)
518 }
519 #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear.\\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"]
520 #[inline(always)]
521 pub fn write_error(&self) -> WRITE_ERROR_R {
522 WRITE_ERROR_R::new(((self.bits >> 29) & 0x01) != 0)
523 }
524 #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."]
525 #[inline(always)]
526 pub fn busy(&self) -> BUSY_R {
527 BUSY_R::new(((self.bits >> 24) & 0x01) != 0)
528 }
529 #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n This allows checksum to be enabled or disabled on a per-control- block basis."]
530 #[inline(always)]
531 pub fn sniff_en(&self) -> SNIFF_EN_R {
532 SNIFF_EN_R::new(((self.bits >> 23) & 0x01) != 0)
533 }
534 #[doc = "Bit 22 - Apply byte-swap transformation to DMA data.\\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
535 #[inline(always)]
536 pub fn bswap(&self) -> BSWAP_R {
537 BSWAP_R::new(((self.bits >> 22) & 0x01) != 0)
538 }
539 #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
540 #[inline(always)]
541 pub fn irq_quiet(&self) -> IRQ_QUIET_R {
542 IRQ_QUIET_R::new(((self.bits >> 21) & 0x01) != 0)
543 }
544 #[doc = "Bits 15:20 - Select a Transfer Request signal.\\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n 0x0 to 0x3a -> select DREQ n as TREQ"]
545 #[inline(always)]
546 pub fn treq_sel(&self) -> TREQ_SEL_R {
547 TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8)
548 }
549 #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\\n Reset value is equal to channel number (6)."]
550 #[inline(always)]
551 pub fn chain_to(&self) -> CHAIN_TO_R {
552 CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8)
553 }
554 #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses.\\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
555 #[inline(always)]
556 pub fn ring_sel(&self) -> RING_SEL_R {
557 RING_SEL_R::new(((self.bits >> 10) & 0x01) != 0)
558 }
559 #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
560 #[inline(always)]
561 pub fn ring_size(&self) -> RING_SIZE_R {
562 RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8)
563 }
564 #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n Generally this should be disabled for memory-to-peripheral transfers."]
565 #[inline(always)]
566 pub fn incr_write(&self) -> INCR_WRITE_R {
567 INCR_WRITE_R::new(((self.bits >> 5) & 0x01) != 0)
568 }
569 #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n Generally this should be disabled for peripheral-to-memory transfers."]
570 #[inline(always)]
571 pub fn incr_read(&self) -> INCR_READ_R {
572 INCR_READ_R::new(((self.bits >> 4) & 0x01) != 0)
573 }
574 #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
575 #[inline(always)]
576 pub fn data_size(&self) -> DATA_SIZE_R {
577 DATA_SIZE_R::new(((self.bits >> 2) & 0x03) as u8)
578 }
579 #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
580 #[inline(always)]
581 pub fn high_priority(&self) -> HIGH_PRIORITY_R {
582 HIGH_PRIORITY_R::new(((self.bits >> 1) & 0x01) != 0)
583 }
584 #[doc = "Bit 0 - DMA Channel Enable.\\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
585 #[inline(always)]
586 pub fn en(&self) -> EN_R {
587 EN_R::new((self.bits & 0x01) != 0)
588 }
589}
590impl W {
591 #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear.\\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"]
592 #[inline(always)]
593 pub fn read_error(&mut self) -> READ_ERROR_W {
594 READ_ERROR_W { w: self }
595 }
596 #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear.\\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"]
597 #[inline(always)]
598 pub fn write_error(&mut self) -> WRITE_ERROR_W {
599 WRITE_ERROR_W { w: self }
600 }
601 #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n This allows checksum to be enabled or disabled on a per-control- block basis."]
602 #[inline(always)]
603 pub fn sniff_en(&mut self) -> SNIFF_EN_W {
604 SNIFF_EN_W { w: self }
605 }
606 #[doc = "Bit 22 - Apply byte-swap transformation to DMA data.\\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
607 #[inline(always)]
608 pub fn bswap(&mut self) -> BSWAP_W {
609 BSWAP_W { w: self }
610 }
611 #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
612 #[inline(always)]
613 pub fn irq_quiet(&mut self) -> IRQ_QUIET_W {
614 IRQ_QUIET_W { w: self }
615 }
616 #[doc = "Bits 15:20 - Select a Transfer Request signal.\\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n 0x0 to 0x3a -> select DREQ n as TREQ"]
617 #[inline(always)]
618 pub fn treq_sel(&mut self) -> TREQ_SEL_W {
619 TREQ_SEL_W { w: self }
620 }
621 #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\\n Reset value is equal to channel number (6)."]
622 #[inline(always)]
623 pub fn chain_to(&mut self) -> CHAIN_TO_W {
624 CHAIN_TO_W { w: self }
625 }
626 #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses.\\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
627 #[inline(always)]
628 pub fn ring_sel(&mut self) -> RING_SEL_W {
629 RING_SEL_W { w: self }
630 }
631 #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
632 #[inline(always)]
633 pub fn ring_size(&mut self) -> RING_SIZE_W {
634 RING_SIZE_W { w: self }
635 }
636 #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n Generally this should be disabled for memory-to-peripheral transfers."]
637 #[inline(always)]
638 pub fn incr_write(&mut self) -> INCR_WRITE_W {
639 INCR_WRITE_W { w: self }
640 }
641 #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n Generally this should be disabled for peripheral-to-memory transfers."]
642 #[inline(always)]
643 pub fn incr_read(&mut self) -> INCR_READ_W {
644 INCR_READ_W { w: self }
645 }
646 #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
647 #[inline(always)]
648 pub fn data_size(&mut self) -> DATA_SIZE_W {
649 DATA_SIZE_W { w: self }
650 }
651 #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
652 #[inline(always)]
653 pub fn high_priority(&mut self) -> HIGH_PRIORITY_W {
654 HIGH_PRIORITY_W { w: self }
655 }
656 #[doc = "Bit 0 - DMA Channel Enable.\\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
657 #[inline(always)]
658 pub fn en(&mut self) -> EN_W {
659 EN_W { w: self }
660 }
661}