[−][src]Struct rp2040::timer::RegisterBlock
Register block
Fields
timehw: TIMEHW
0x00 - Write to bits 63:32 of time\n always write timelw before timehw
timelw: TIMELW
0x04 - Write to bits 31:0 of time\n writes do not get copied to time until timehw is written
timehr: TIMEHR
0x08 - Read from bits 63:32 of time\n always read timelr before timehr
timelr: TIMELR
0x0c - Read from bits 31:0 of time
alarm0: ALARM0
0x10 - Arm alarm 0, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register.
alarm1: ALARM1
0x14 - Arm alarm 1, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register.
alarm2: ALARM2
0x18 - Arm alarm 2, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register.
alarm3: ALARM3
0x1c - Arm alarm 3, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register.
armed: ARMED
0x20 - Indicates the armed/disarmed status of each alarm.\n A write to the corresponding ALARMx register arms the alarm.\n Alarms automatically disarm upon firing, but writing ones here\n will disarm immediately without waiting to fire.
timerawh: TIMERAWH
0x24 - Raw read from bits 63:32 of time (no side effects)
timerawl: TIMERAWL
0x28 - Raw read from bits 31:0 of time (no side effects)
dbgpause: DBGPAUSE
0x2c - Set bits high to enable pause when the corresponding debug ports are active
pause: PAUSE
0x30 - Set high to pause the timer
intr: INTR
0x34 - Raw Interrupts
inte: INTE
0x38 - Interrupt Enable
intf: INTF
0x3c - Interrupt Force
ints: INTS
0x40 - Interrupt status after masking & forcing
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