[−][src]Struct rp2040::generic::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Implementations

`impl<U, T> R<U, T> where U: Copy,` [src]

`pub fn bits(&self) -> U`[src]

Read raw bits from register/field

`impl<FI> R<bool, FI>`[src]

`pub fn bit(&self) -> bool`[src]

Value of the field as raw bits

`pub fn bit_is_clear(&self) -> bool`[src]

Returns true if the bit is clear (0)

`pub fn bit_is_set(&self) -> bool`[src]

Returns true if the bit is set (1)

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn power_down(&self) -> POWER_DOWN_R`[src]

Bit 3 - When 1, the cache memories are powered down. They retain state,\n but can not be accessed. This reduces static power dissipation.\n Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n be enabled when powered down.\n Cache-as-SRAM accesses will produce a bus error response when\n the cache is powered down.

`pub fn err_badwrite(&self) -> ERR_BADWRITE_R`[src]

Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating)\n will produce a bus fault. When 0, these writes are silently ignored.\n In either case, writes to the 0x0 alias will deallocate on tag match,\n as usual.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses\n will go straight to the flash, without querying the cache. When enabled,\n cacheable XIP accesses will query the cache, and the flash will\n not be accessed if the tag matches and the valid bit is set.\n\n If the cache is enabled, cache-as-SRAM accesses have no effect on the\n cache data RAM, and will produce a bus error response.

`impl R<u32, Reg<u32, _FLUSH>>`[src]

`pub fn flush(&self) -> FLUSH_R`[src]

Bit 0 - Write 1 to flush the cache. This clears the tag memory, but\n the data memory retains its contents. (This means cache-as-SRAM\n contents is not affected by flush or reset.)\n Reading will hold the bus (stall the processor) until the flush\n completes. Alternatively STAT can be polled until completion.

`impl R<u32, Reg<u32, _STAT>>`[src]

`pub fn fifo_full(&self) -> FIFO_FULL_R`[src]

Bit 2 - When 1, indicates the XIP streaming FIFO is completely full.\n The streaming FIFO is 2 entries deep, so the full and empty\n flag allow its level to be ascertained.

`pub fn fifo_empty(&self) -> FIFO_EMPTY_R`[src]

Bit 1 - When 1, indicates the XIP streaming FIFO is completely empty.

`pub fn flush_ready(&self) -> FLUSH_READY_R`[src]

Bit 0 - Reads as 0 while a cache flush is in progress, and 1 otherwise.\n The cache is flushed whenever the XIP block is reset, and also\n when requested via the FLUSH register.

`impl R<u32, Reg<u32, _STREAM_ADDR>>`[src]

`pub fn stream_addr(&self) -> STREAM_ADDR_R`[src]

Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO.\n Increments automatically after each flash access.\n Write the initial access address here before starting a streaming read.

`impl R<u32, Reg<u32, _STREAM_CTR>>`[src]

`pub fn stream_ctr(&self) -> STREAM_CTR_R`[src]

Bits 0:21 - Write a nonzero value to start a streaming read. This will then\n progress in the background, using flash idle cycles to transfer\n a linear data block from flash to the streaming FIFO.\n Decrements automatically (1 at a time) as the stream\n progresses, and halts on reaching 0.\n Write 0 to halt an in-progress stream, and discard any in-flight\n read, so that a new stream can immediately be started (after\n draining the FIFO and reinitialising STREAM_ADDR)

`impl R<u8, SPI_FRF_A>`[src]

`pub fn variant(&self) -> Variant<u8, SPI_FRF_A>`[src]

Get enumerated values variant

`pub fn is_std(&self) -> bool`[src]

Checks if the value of the field is STD

`pub fn is_dual(&self) -> bool`[src]

Checks if the value of the field is DUAL

`pub fn is_quad(&self) -> bool`[src]

Checks if the value of the field is QUAD

`impl R<u8, TMOD_A>`[src]

`pub fn variant(&self) -> TMOD_A`[src]

Get enumerated values variant

`pub fn is_tx_and_rx(&self) -> bool`[src]

Checks if the value of the field is TX_AND_RX

`pub fn is_tx_only(&self) -> bool`[src]

Checks if the value of the field is TX_ONLY

`pub fn is_rx_only(&self) -> bool`[src]

Checks if the value of the field is RX_ONLY

`pub fn is_eeprom_read(&self) -> bool`[src]

Checks if the value of the field is EEPROM_READ

`impl R<u32, Reg<u32, _CTRLR0>>`[src]

`pub fn sste(&self) -> SSTE_R`[src]

Bit 24 - Slave select toggle enable

`pub fn spi_frf(&self) -> SPI_FRF_R`[src]

Bits 21:22 - SPI frame format

`pub fn dfs_32(&self) -> DFS_32_R`[src]

Bits 16:20 - Data frame size in 32b transfer mode\n Value of n -> n+1 clocks per frame.

`pub fn cfs(&self) -> CFS_R`[src]

Bits 12:15 - Control frame size\n Value of n -> n+1 clocks per frame.

`pub fn srl(&self) -> SRL_R`[src]

Bit 11 - Shift register loop (test mode)

`pub fn slv_oe(&self) -> SLV_OE_R`[src]

Bit 10 - Slave output enable

`pub fn tmod(&self) -> TMOD_R`[src]

Bits 8:9 - Transfer mode

`pub fn scpol(&self) -> SCPOL_R`[src]

Bit 7 - Serial clock polarity

`pub fn scph(&self) -> SCPH_R`[src]

Bit 6 - Serial clock phase

`pub fn frf(&self) -> FRF_R`[src]

Bits 4:5 - Frame format

`pub fn dfs(&self) -> DFS_R`[src]

Bits 0:3 - Data frame size

`impl R<u32, Reg<u32, _CTRLR1>>`[src]

`pub fn ndf(&self) -> NDF_R`[src]

Bits 0:15 - Number of data frames

`impl R<u32, Reg<u32, _SSIENR>>`[src]

`pub fn ssi_en(&self) -> SSI_EN_R`[src]

Bit 0 - SSI enable

`impl R<u32, Reg<u32, _MWCR>>`[src]

`pub fn mhs(&self) -> MHS_R`[src]

Bit 2 - Microwire handshaking

`pub fn mdd(&self) -> MDD_R`[src]

Bit 1 - Microwire control

`pub fn mwmod(&self) -> MWMOD_R`[src]

Bit 0 - Microwire transfer mode

`impl R<u32, Reg<u32, _SER>>`[src]

`pub fn ser(&self) -> SER_R`[src]

Bit 0 - For each bit:\n 0 -> slave not selected\n 1 -> slave selected

`impl R<u32, Reg<u32, _BAUDR>>`[src]

`pub fn sckdv(&self) -> SCKDV_R`[src]

Bits 0:15 - SSI clock divider

`impl R<u32, Reg<u32, _TXFTLR>>`[src]

`pub fn tft(&self) -> TFT_R`[src]

Bits 0:7 - Transmit FIFO threshold

`impl R<u32, Reg<u32, _RXFTLR>>`[src]

`pub fn rft(&self) -> RFT_R`[src]

Bits 0:7 - Receive FIFO threshold

`impl R<u32, Reg<u32, _TXFLR>>`[src]

`pub fn tftfl(&self) -> TFTFL_R`[src]

Bits 0:7 - Transmit FIFO level

`impl R<u32, Reg<u32, _RXFLR>>`[src]

`pub fn rxtfl(&self) -> RXTFL_R`[src]

Bits 0:7 - Receive FIFO level

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn dcol(&self) -> DCOL_R`[src]

Bit 6 - Data collision error

`pub fn txe(&self) -> TXE_R`[src]

Bit 5 - Transmission error

`pub fn rff(&self) -> RFF_R`[src]

Bit 4 - Receive FIFO full

`pub fn rfne(&self) -> RFNE_R`[src]

Bit 3 - Receive FIFO not empty

`pub fn tfe(&self) -> TFE_R`[src]

Bit 2 - Transmit FIFO empty

`pub fn tfnf(&self) -> TFNF_R`[src]

Bit 1 - Transmit FIFO not full

`pub fn busy(&self) -> BUSY_R`[src]

Bit 0 - SSI busy flag

`impl R<u32, Reg<u32, _IMR>>`[src]

`pub fn mstim(&self) -> MSTIM_R`[src]

Bit 5 - Multi-master contention interrupt mask

`pub fn rxfim(&self) -> RXFIM_R`[src]

Bit 4 - Receive FIFO full interrupt mask

`pub fn rxoim(&self) -> RXOIM_R`[src]

Bit 3 - Receive FIFO overflow interrupt mask

`pub fn rxuim(&self) -> RXUIM_R`[src]

Bit 2 - Receive FIFO underflow interrupt mask

`pub fn txoim(&self) -> TXOIM_R`[src]

Bit 1 - Transmit FIFO overflow interrupt mask

`pub fn txeim(&self) -> TXEIM_R`[src]

Bit 0 - Transmit FIFO empty interrupt mask

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn mstis(&self) -> MSTIS_R`[src]

Bit 5 - Multi-master contention interrupt status

`pub fn rxfis(&self) -> RXFIS_R`[src]

Bit 4 - Receive FIFO full interrupt status

`pub fn rxois(&self) -> RXOIS_R`[src]

Bit 3 - Receive FIFO overflow interrupt status

`pub fn rxuis(&self) -> RXUIS_R`[src]

Bit 2 - Receive FIFO underflow interrupt status

`pub fn txois(&self) -> TXOIS_R`[src]

Bit 1 - Transmit FIFO overflow interrupt status

`pub fn txeis(&self) -> TXEIS_R`[src]

Bit 0 - Transmit FIFO empty interrupt status

`impl R<u32, Reg<u32, _RISR>>`[src]

`pub fn mstir(&self) -> MSTIR_R`[src]

Bit 5 - Multi-master contention raw interrupt status

`pub fn rxfir(&self) -> RXFIR_R`[src]

Bit 4 - Receive FIFO full raw interrupt status

`pub fn rxoir(&self) -> RXOIR_R`[src]

Bit 3 - Receive FIFO overflow raw interrupt status

`pub fn rxuir(&self) -> RXUIR_R`[src]

Bit 2 - Receive FIFO underflow raw interrupt status

`pub fn txoir(&self) -> TXOIR_R`[src]

Bit 1 - Transmit FIFO overflow raw interrupt status

`pub fn txeir(&self) -> TXEIR_R`[src]

Bit 0 - Transmit FIFO empty raw interrupt status

`impl R<u32, Reg<u32, _TXOICR>>`[src]

`pub fn txoicr(&self) -> TXOICR_R`[src]

Bit 0 - Clear-on-read transmit FIFO overflow interrupt

`impl R<u32, Reg<u32, _RXOICR>>`[src]

`pub fn rxoicr(&self) -> RXOICR_R`[src]

Bit 0 - Clear-on-read receive FIFO overflow interrupt

`impl R<u32, Reg<u32, _RXUICR>>`[src]

`pub fn rxuicr(&self) -> RXUICR_R`[src]

Bit 0 - Clear-on-read receive FIFO underflow interrupt

`impl R<u32, Reg<u32, _MSTICR>>`[src]

`pub fn msticr(&self) -> MSTICR_R`[src]

Bit 0 - Clear-on-read multi-master contention interrupt

`impl R<u32, Reg<u32, _ICR>>`[src]

`pub fn icr(&self) -> ICR_R`[src]

Bit 0 - Clear-on-read all active interrupts

`impl R<u32, Reg<u32, _DMACR>>`[src]

`pub fn tdmae(&self) -> TDMAE_R`[src]

Bit 1 - Transmit DMA enable

`pub fn rdmae(&self) -> RDMAE_R`[src]

Bit 0 - Receive DMA enable

`impl R<u32, Reg<u32, _DMATDLR>>`[src]

`pub fn dmatdl(&self) -> DMATDL_R`[src]

Bits 0:7 - Transmit data watermark level

`impl R<u32, Reg<u32, _DMARDLR>>`[src]

`pub fn dmardl(&self) -> DMARDL_R`[src]

Bits 0:7 - Receive data watermark level (DMARDLR+1)

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idcode(&self) -> IDCODE_R`[src]

Bits 0:31 - Peripheral dentification code

`impl R<u32, Reg<u32, _SSI_VERSION_ID>>`[src]

`pub fn ssi_comp_version(&self) -> SSI_COMP_VERSION_R`[src]

Bits 0:31 - SNPS component version (format X.YY)

`impl R<u32, Reg<u32, _DR0>>`[src]

`pub fn dr(&self) -> DR_R`[src]

Bits 0:31 - First data register of 36

`impl R<u32, Reg<u32, _RX_SAMPLE_DLY>>`[src]

`pub fn rsd(&self) -> RSD_R`[src]

Bits 0:7 - RXD sample delay (in SCLK cycles)

`impl R<u8, INST_L_A>`[src]

`pub fn variant(&self) -> INST_L_A`[src]

Get enumerated values variant

`pub fn is_none(&self) -> bool`[src]

Checks if the value of the field is NONE

`pub fn is_4b(&self) -> bool`[src]

Checks if the value of the field is _4B

`pub fn is_8b(&self) -> bool`[src]

Checks if the value of the field is _8B

`pub fn is_16b(&self) -> bool`[src]

Checks if the value of the field is _16B

`impl R<u8, TRANS_TYPE_A>`[src]

`pub fn variant(&self) -> Variant<u8, TRANS_TYPE_A>`[src]

Get enumerated values variant

`pub fn is_1c1a(&self) -> bool`[src]

Checks if the value of the field is _1C1A

`pub fn is_1c2a(&self) -> bool`[src]

Checks if the value of the field is _1C2A

`pub fn is_2c2a(&self) -> bool`[src]

Checks if the value of the field is _2C2A

`impl R<u32, Reg<u32, _SPI_CTRLR0>>`[src]

`pub fn xip_cmd(&self) -> XIP_CMD_R`[src]

Bits 24:31 - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)

`pub fn spi_rxds_en(&self) -> SPI_RXDS_EN_R`[src]

Bit 18 - Read data strobe enable

`pub fn inst_ddr_en(&self) -> INST_DDR_EN_R`[src]

Bit 17 - Instruction DDR transfer enable

`pub fn spi_ddr_en(&self) -> SPI_DDR_EN_R`[src]

Bit 16 - SPI DDR transfer enable

`pub fn wait_cycles(&self) -> WAIT_CYCLES_R`[src]

Bits 11:15 - Wait cycles between control frame transmit and data reception (in SCLK cycles)

`pub fn inst_l(&self) -> INST_L_R`[src]

Bits 8:9 - Instruction length (0/4/8/16b)

`pub fn addr_l(&self) -> ADDR_L_R`[src]

Bits 2:5 - Address length (0b-60b in 4b increments)

`pub fn trans_type(&self) -> TRANS_TYPE_R`[src]

Bits 0:1 - Address and instruction transfer format

`impl R<u32, Reg<u32, _TXD_DRIVE_EDGE>>`[src]

`pub fn tde(&self) -> TDE_R`[src]

Bits 0:7 - TXD drive edge

`impl R<u32, Reg<u32, _CHIP_ID>>`[src]

`pub fn revision(&self) -> REVISION_R`[src]

Bits 28:31

`pub fn part(&self) -> PART_R`[src]

Bits 12:27

`pub fn manufacturer(&self) -> MANUFACTURER_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _PLATFORM>>`[src]

`pub fn asic(&self) -> ASIC_R`[src]

Bit 1

`pub fn fpga(&self) -> FPGA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC_CONFIG>>`[src]

`pub fn proc1_dap_instid(&self) -> PROC1_DAP_INSTID_R`[src]

Bits 28:31 - Configure proc1 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP

`pub fn proc0_dap_instid(&self) -> PROC0_DAP_INSTID_R`[src]

Bits 24:27 - Configure proc0 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP

`pub fn proc1_halted(&self) -> PROC1_HALTED_R`[src]

Bit 1 - Indication that proc1 has halted

`pub fn proc0_halted(&self) -> PROC0_HALTED_R`[src]

Bit 0 - Indication that proc0 has halted

`impl R<u32, Reg<u32, _PROC_IN_SYNC_BYPASS>>`[src]

`pub fn proc_in_sync_bypass(&self) -> PROC_IN_SYNC_BYPASS_R`[src]

Bits 0:29

`impl R<u32, Reg<u32, _PROC_IN_SYNC_BYPASS_HI>>`[src]

`pub fn proc_in_sync_bypass_hi(&self) -> PROC_IN_SYNC_BYPASS_HI_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _DBGFORCE>>`[src]

`pub fn proc1_attach(&self) -> PROC1_ATTACH_R`[src]

Bit 7 - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.

`pub fn proc1_swclk(&self) -> PROC1_SWCLK_R`[src]

Bit 6 - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set

`pub fn proc1_swdi(&self) -> PROC1_SWDI_R`[src]

Bit 5 - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set

`pub fn proc1_swdo(&self) -> PROC1_SWDO_R`[src]

Bit 4 - Observe the value of processor 1 SWDIO output.

`pub fn proc0_attach(&self) -> PROC0_ATTACH_R`[src]

Bit 3 - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.

`pub fn proc0_swclk(&self) -> PROC0_SWCLK_R`[src]

Bit 2 - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set

`pub fn proc0_swdi(&self) -> PROC0_SWDI_R`[src]

Bit 1 - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set

`pub fn proc0_swdo(&self) -> PROC0_SWDO_R`[src]

Bit 0 - Observe the value of processor 0 SWDIO output.

`impl R<u32, Reg<u32, _MEMPOWERDOWN>>`[src]

`pub fn rom(&self) -> ROM_R`[src]

Bit 7

`pub fn usb(&self) -> USB_R`[src]

Bit 6

`pub fn sram5(&self) -> SRAM5_R`[src]

Bit 5

`pub fn sram4(&self) -> SRAM4_R`[src]

Bit 4

`pub fn sram3(&self) -> SRAM3_R`[src]

Bit 3

`pub fn sram2(&self) -> SRAM2_R`[src]

Bit 2

`pub fn sram1(&self) -> SRAM1_R`[src]

Bit 1

`pub fn sram0(&self) -> SRAM0_R`[src]

Bit 0

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_rosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clk_sys(&self) -> bool`[src]

Checks if the value of the field is CLK_SYS

`pub fn is_clk_usb(&self) -> bool`[src]

Checks if the value of the field is CLK_USB

`pub fn is_clk_adc(&self) -> bool`[src]

Checks if the value of the field is CLK_ADC

`pub fn is_clk_rtc(&self) -> bool`[src]

Checks if the value of the field is CLK_RTC

`pub fn is_clk_ref(&self) -> bool`[src]

Checks if the value of the field is CLK_REF

`impl R<u32, Reg<u32, _CLK_GPOUT0_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn dc50(&self) -> DC50_R`[src]

Bit 12 - Enables duty cycle correction for odd divisors

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_GPOUT0_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional component of the divisor

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_rosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clk_sys(&self) -> bool`[src]

Checks if the value of the field is CLK_SYS

`pub fn is_clk_usb(&self) -> bool`[src]

Checks if the value of the field is CLK_USB

`pub fn is_clk_adc(&self) -> bool`[src]

Checks if the value of the field is CLK_ADC

`pub fn is_clk_rtc(&self) -> bool`[src]

Checks if the value of the field is CLK_RTC

`pub fn is_clk_ref(&self) -> bool`[src]

Checks if the value of the field is CLK_REF

`impl R<u32, Reg<u32, _CLK_GPOUT1_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn dc50(&self) -> DC50_R`[src]

Bit 12 - Enables duty cycle correction for odd divisors

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_GPOUT1_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional component of the divisor

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clk_sys(&self) -> bool`[src]

Checks if the value of the field is CLK_SYS

`pub fn is_clk_usb(&self) -> bool`[src]

Checks if the value of the field is CLK_USB

`pub fn is_clk_adc(&self) -> bool`[src]

Checks if the value of the field is CLK_ADC

`pub fn is_clk_rtc(&self) -> bool`[src]

Checks if the value of the field is CLK_RTC

`pub fn is_clk_ref(&self) -> bool`[src]

Checks if the value of the field is CLK_REF

`impl R<u32, Reg<u32, _CLK_GPOUT2_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn dc50(&self) -> DC50_R`[src]

Bit 12 - Enables duty cycle correction for odd divisors

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_GPOUT2_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional component of the divisor

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clk_sys(&self) -> bool`[src]

Checks if the value of the field is CLK_SYS

`pub fn is_clk_usb(&self) -> bool`[src]

Checks if the value of the field is CLK_USB

`pub fn is_clk_adc(&self) -> bool`[src]

Checks if the value of the field is CLK_ADC

`pub fn is_clk_rtc(&self) -> bool`[src]

Checks if the value of the field is CLK_RTC

`pub fn is_clk_ref(&self) -> bool`[src]

Checks if the value of the field is CLK_REF

`impl R<u32, Reg<u32, _CLK_GPOUT3_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn dc50(&self) -> DC50_R`[src]

Bit 12 - Enables duty cycle correction for odd divisors

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_GPOUT3_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional component of the divisor

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`impl R<u8, SRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, SRC_A>`[src]

Get enumerated values variant

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_clksrc_clk_ref_aux(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_CLK_REF_AUX

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`impl R<u32, Reg<u32, _CLK_REF_CTRL>>`[src]

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:6 - Selects the auxiliary clock source, will glitch when switching

`pub fn src(&self) -> SRC_R`[src]

Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly

`impl R<u32, Reg<u32, _CLK_REF_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_rosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`impl R<bool, SRC_A>`[src]

`pub fn variant(&self) -> SRC_A`[src]

Get enumerated values variant

`pub fn is_clk_ref(&self) -> bool`[src]

Checks if the value of the field is CLK_REF

`pub fn is_clksrc_clk_sys_aux(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_CLK_SYS_AUX

`impl R<u32, Reg<u32, _CLK_SYS_CTRL>>`[src]

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

`pub fn src(&self) -> SRC_R`[src]

Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly

`impl R<u32, Reg<u32, _CLK_SYS_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional component of the divisor

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clk_sys(&self) -> bool`[src]

Checks if the value of the field is CLK_SYS

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`impl R<u32, Reg<u32, _CLK_PERI_CTRL>>`[src]

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`impl R<u32, Reg<u32, _CLK_USB_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_USB_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`impl R<u32, Reg<u32, _CLK_ADC_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_ADC_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16

`impl R<u8, AUXSRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, AUXSRC_A>`[src]

Get enumerated values variant

`pub fn is_clksrc_pll_usb(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_USB

`pub fn is_clksrc_pll_sys(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_PLL_SYS

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`impl R<u32, Reg<u32, _CLK_RTC_CTRL>>`[src]

`pub fn nudge(&self) -> NUDGE_R`[src]

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time

`pub fn phase(&self) -> PHASE_R`[src]

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 11 - Starts and stops the clock generator cleanly

`pub fn kill(&self) -> KILL_R`[src]

Bit 10 - Asynchronously kills the clock generator

`pub fn auxsrc(&self) -> AUXSRC_R`[src]

Bits 5:7 - Selects the auxiliary clock source, will glitch when switching

`impl R<u32, Reg<u32, _CLK_RTC_DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional component of the divisor

`impl R<u32, Reg<u32, _CLK_SYS_RESUS_CTRL>>`[src]

`pub fn clear(&self) -> CLEAR_R`[src]

Bit 16 - For clearing the resus after the fault that triggered it has been corrected

`pub fn frce(&self) -> FRCE_R`[src]

Bit 12 - Force a resus, for test purposes only

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 8 - Enable resus

`pub fn timeout(&self) -> TIMEOUT_R`[src]

Bits 0:7 - This is expressed as a number of clk_ref cycles\n and must be >= 2x clk_ref_freq/min_clk_tst_freq

`impl R<u32, Reg<u32, _CLK_SYS_RESUS_STATUS>>`[src]

`pub fn resussed(&self) -> RESUSSED_R`[src]

Bit 0 - Clock has been resuscitated, correct the error then send ctrl_clear=1

`impl R<u32, Reg<u32, _FC0_REF_KHZ>>`[src]

`pub fn fc0_ref_khz(&self) -> FC0_REF_KHZ_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _FC0_MIN_KHZ>>`[src]

`pub fn fc0_min_khz(&self) -> FC0_MIN_KHZ_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _FC0_MAX_KHZ>>`[src]

`pub fn fc0_max_khz(&self) -> FC0_MAX_KHZ_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _FC0_DELAY>>`[src]

`pub fn fc0_delay(&self) -> FC0_DELAY_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _FC0_INTERVAL>>`[src]

`pub fn fc0_interval(&self) -> FC0_INTERVAL_R`[src]

Bits 0:3

`impl R<u8, FC0_SRC_A>`[src]

`pub fn variant(&self) -> Variant<u8, FC0_SRC_A>`[src]

Get enumerated values variant

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`pub fn is_pll_sys_clksrc_primary(&self) -> bool`[src]

Checks if the value of the field is PLL_SYS_CLKSRC_PRIMARY

`pub fn is_pll_usb_clksrc_primary(&self) -> bool`[src]

Checks if the value of the field is PLL_USB_CLKSRC_PRIMARY

`pub fn is_rosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC

`pub fn is_rosc_clksrc_ph(&self) -> bool`[src]

Checks if the value of the field is ROSC_CLKSRC_PH

`pub fn is_xosc_clksrc(&self) -> bool`[src]

Checks if the value of the field is XOSC_CLKSRC

`pub fn is_clksrc_gpin0(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN0

`pub fn is_clksrc_gpin1(&self) -> bool`[src]

Checks if the value of the field is CLKSRC_GPIN1

`pub fn is_clk_ref(&self) -> bool`[src]

Checks if the value of the field is CLK_REF

`pub fn is_clk_sys(&self) -> bool`[src]

Checks if the value of the field is CLK_SYS

`pub fn is_clk_peri(&self) -> bool`[src]

Checks if the value of the field is CLK_PERI

`pub fn is_clk_usb(&self) -> bool`[src]

Checks if the value of the field is CLK_USB

`pub fn is_clk_adc(&self) -> bool`[src]

Checks if the value of the field is CLK_ADC

`pub fn is_clk_rtc(&self) -> bool`[src]

Checks if the value of the field is CLK_RTC

`impl R<u32, Reg<u32, _FC0_SRC>>`[src]

`pub fn fc0_src(&self) -> FC0_SRC_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _FC0_STATUS>>`[src]

`pub fn died(&self) -> DIED_R`[src]

Bit 28 - Test clock stopped during test

`pub fn fast(&self) -> FAST_R`[src]

Bit 24 - Test clock faster than expected, only valid when status_done=1

`pub fn slow(&self) -> SLOW_R`[src]

Bit 20 - Test clock slower than expected, only valid when status_done=1

`pub fn fail(&self) -> FAIL_R`[src]

Bit 16 - Test failed

`pub fn waiting(&self) -> WAITING_R`[src]

Bit 12 - Waiting for test clock to start

`pub fn running(&self) -> RUNNING_R`[src]

Bit 8 - Test running

`pub fn done(&self) -> DONE_R`[src]

Bit 4 - Test complete

`pub fn pass(&self) -> PASS_R`[src]

Bit 0 - Test passed

`impl R<u32, Reg<u32, _FC0_RESULT>>`[src]

`pub fn khz(&self) -> KHZ_R`[src]

Bits 5:29

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _WAKE_EN0>>`[src]

`pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R`[src]

Bit 31

`pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R`[src]

Bit 30

`pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R`[src]

Bit 29

`pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R`[src]

Bit 28

`pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R`[src]

Bit 27

`pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R`[src]

Bit 26

`pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R`[src]

Bit 25

`pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R`[src]

Bit 24

`pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R`[src]

Bit 23

`pub fn clk_sys_rtc(&self) -> CLK_SYS_RTC_R`[src]

Bit 22

`pub fn clk_rtc_rtc(&self) -> CLK_RTC_RTC_R`[src]

Bit 21

`pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R`[src]

Bit 20

`pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R`[src]

Bit 19

`pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R`[src]

Bit 18

`pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R`[src]

Bit 17

`pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R`[src]

Bit 16

`pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R`[src]

Bit 15

`pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R`[src]

Bit 14

`pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R`[src]

Bit 13

`pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R`[src]

Bit 12

`pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R`[src]

Bit 11

`pub fn clk_sys_vreg_and_chip_reset(&self) -> CLK_SYS_VREG_AND_CHIP_RESET_R`[src]

Bit 10

`pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R`[src]

Bit 9

`pub fn clk_sys_io(&self) -> CLK_SYS_IO_R`[src]

Bit 8

`pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R`[src]

Bit 7

`pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R`[src]

Bit 6

`pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R`[src]

Bit 5

`pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R`[src]

Bit 4

`pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R`[src]

Bit 3

`pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R`[src]

Bit 2

`pub fn clk_adc_adc(&self) -> CLK_ADC_ADC_R`[src]

Bit 1

`pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _WAKE_EN1>>`[src]

`pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R`[src]

Bit 14

`pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R`[src]

Bit 13

`pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R`[src]

Bit 12

`pub fn clk_usb_usbctrl(&self) -> CLK_USB_USBCTRL_R`[src]

Bit 11

`pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R`[src]

Bit 10

`pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R`[src]

Bit 9

`pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R`[src]

Bit 8

`pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R`[src]

Bit 7

`pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R`[src]

Bit 6

`pub fn clk_sys_timer(&self) -> CLK_SYS_TIMER_R`[src]

Bit 5

`pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R`[src]

Bit 4

`pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R`[src]

Bit 3

`pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R`[src]

Bit 2

`pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R`[src]

Bit 1

`pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SLEEP_EN0>>`[src]

`pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R`[src]

Bit 31

`pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R`[src]

Bit 30

`pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R`[src]

Bit 29

`pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R`[src]

Bit 28

`pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R`[src]

Bit 27

`pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R`[src]

Bit 26

`pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R`[src]

Bit 25

`pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R`[src]

Bit 24

`pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R`[src]

Bit 23

`pub fn clk_sys_rtc(&self) -> CLK_SYS_RTC_R`[src]

Bit 22

`pub fn clk_rtc_rtc(&self) -> CLK_RTC_RTC_R`[src]

Bit 21

`pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R`[src]

Bit 20

`pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R`[src]

Bit 19

`pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R`[src]

Bit 18

`pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R`[src]

Bit 17

`pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R`[src]

Bit 16

`pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R`[src]

Bit 15

`pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R`[src]

Bit 14

`pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R`[src]

Bit 13

`pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R`[src]

Bit 12

`pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R`[src]

Bit 11

`pub fn clk_sys_vreg_and_chip_reset(&self) -> CLK_SYS_VREG_AND_CHIP_RESET_R`[src]

Bit 10

`pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R`[src]

Bit 9

`pub fn clk_sys_io(&self) -> CLK_SYS_IO_R`[src]

Bit 8

`pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R`[src]

Bit 7

`pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R`[src]

Bit 6

`pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R`[src]

Bit 5

`pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R`[src]

Bit 4

`pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R`[src]

Bit 3

`pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R`[src]

Bit 2

`pub fn clk_adc_adc(&self) -> CLK_ADC_ADC_R`[src]

Bit 1

`pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SLEEP_EN1>>`[src]

`pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R`[src]

Bit 14

`pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R`[src]

Bit 13

`pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R`[src]

Bit 12

`pub fn clk_usb_usbctrl(&self) -> CLK_USB_USBCTRL_R`[src]

Bit 11

`pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R`[src]

Bit 10

`pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R`[src]

Bit 9

`pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R`[src]

Bit 8

`pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R`[src]

Bit 7

`pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R`[src]

Bit 6

`pub fn clk_sys_timer(&self) -> CLK_SYS_TIMER_R`[src]

Bit 5

`pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R`[src]

Bit 4

`pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R`[src]

Bit 3

`pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R`[src]

Bit 2

`pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R`[src]

Bit 1

`pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ENABLED0>>`[src]

`pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R`[src]

Bit 31

`pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R`[src]

Bit 30

`pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R`[src]

Bit 29

`pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R`[src]

Bit 28

`pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R`[src]

Bit 27

`pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R`[src]

Bit 26

`pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R`[src]

Bit 25

`pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R`[src]

Bit 24

`pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R`[src]

Bit 23

`pub fn clk_sys_rtc(&self) -> CLK_SYS_RTC_R`[src]

Bit 22

`pub fn clk_rtc_rtc(&self) -> CLK_RTC_RTC_R`[src]

Bit 21

`pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R`[src]

Bit 20

`pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R`[src]

Bit 19

`pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R`[src]

Bit 18

`pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R`[src]

Bit 17

`pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R`[src]

Bit 16

`pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R`[src]

Bit 15

`pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R`[src]

Bit 14

`pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R`[src]

Bit 13

`pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R`[src]

Bit 12

`pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R`[src]

Bit 11

`pub fn clk_sys_vreg_and_chip_reset(&self) -> CLK_SYS_VREG_AND_CHIP_RESET_R`[src]

Bit 10

`pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R`[src]

Bit 9

`pub fn clk_sys_io(&self) -> CLK_SYS_IO_R`[src]

Bit 8

`pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R`[src]

Bit 7

`pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R`[src]

Bit 6

`pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R`[src]

Bit 5

`pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R`[src]

Bit 4

`pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R`[src]

Bit 3

`pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R`[src]

Bit 2

`pub fn clk_adc_adc(&self) -> CLK_ADC_ADC_R`[src]

Bit 1

`pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ENABLED1>>`[src]

`pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R`[src]

Bit 14

`pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R`[src]

Bit 13

`pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R`[src]

Bit 12

`pub fn clk_usb_usbctrl(&self) -> CLK_USB_USBCTRL_R`[src]

Bit 11

`pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R`[src]

Bit 10

`pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R`[src]

Bit 9

`pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R`[src]

Bit 8

`pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R`[src]

Bit 7

`pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R`[src]

Bit 6

`pub fn clk_sys_timer(&self) -> CLK_SYS_TIMER_R`[src]

Bit 5

`pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R`[src]

Bit 4

`pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R`[src]

Bit 3

`pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R`[src]

Bit 2

`pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R`[src]

Bit 1

`pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTE>>`[src]

`pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTF>>`[src]

`pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTS>>`[src]

`pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _RESET>>`[src]

`pub fn usbctrl(&self) -> USBCTRL_R`[src]

Bit 24

`pub fn uart1(&self) -> UART1_R`[src]

Bit 23

`pub fn uart0(&self) -> UART0_R`[src]

Bit 22

`pub fn timer(&self) -> TIMER_R`[src]

Bit 21

`pub fn tbman(&self) -> TBMAN_R`[src]

Bit 20

`pub fn sysinfo(&self) -> SYSINFO_R`[src]

Bit 19

`pub fn syscfg(&self) -> SYSCFG_R`[src]

Bit 18

`pub fn spi1(&self) -> SPI1_R`[src]

Bit 17

`pub fn spi0(&self) -> SPI0_R`[src]

Bit 16

`pub fn rtc(&self) -> RTC_R`[src]

Bit 15

`pub fn pwm(&self) -> PWM_R`[src]

Bit 14

`pub fn pll_usb(&self) -> PLL_USB_R`[src]

Bit 13

`pub fn pll_sys(&self) -> PLL_SYS_R`[src]

Bit 12

`pub fn pio1(&self) -> PIO1_R`[src]

Bit 11

`pub fn pio0(&self) -> PIO0_R`[src]

Bit 10

`pub fn pads_qspi(&self) -> PADS_QSPI_R`[src]

Bit 9

`pub fn pads_bank0(&self) -> PADS_BANK0_R`[src]

Bit 8

`pub fn jtag(&self) -> JTAG_R`[src]

Bit 7

`pub fn io_qspi(&self) -> IO_QSPI_R`[src]

Bit 6

`pub fn io_bank0(&self) -> IO_BANK0_R`[src]

Bit 5

`pub fn i2c1(&self) -> I2C1_R`[src]

Bit 4

`pub fn i2c0(&self) -> I2C0_R`[src]

Bit 3

`pub fn dma(&self) -> DMA_R`[src]

Bit 2

`pub fn busctrl(&self) -> BUSCTRL_R`[src]

Bit 1

`pub fn adc(&self) -> ADC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _WDSEL>>`[src]

`pub fn usbctrl(&self) -> USBCTRL_R`[src]

Bit 24

`pub fn uart1(&self) -> UART1_R`[src]

Bit 23

`pub fn uart0(&self) -> UART0_R`[src]

Bit 22

`pub fn timer(&self) -> TIMER_R`[src]

Bit 21

`pub fn tbman(&self) -> TBMAN_R`[src]

Bit 20

`pub fn sysinfo(&self) -> SYSINFO_R`[src]

Bit 19

`pub fn syscfg(&self) -> SYSCFG_R`[src]

Bit 18

`pub fn spi1(&self) -> SPI1_R`[src]

Bit 17

`pub fn spi0(&self) -> SPI0_R`[src]

Bit 16

`pub fn rtc(&self) -> RTC_R`[src]

Bit 15

`pub fn pwm(&self) -> PWM_R`[src]

Bit 14

`pub fn pll_usb(&self) -> PLL_USB_R`[src]

Bit 13

`pub fn pll_sys(&self) -> PLL_SYS_R`[src]

Bit 12

`pub fn pio1(&self) -> PIO1_R`[src]

Bit 11

`pub fn pio0(&self) -> PIO0_R`[src]

Bit 10

`pub fn pads_qspi(&self) -> PADS_QSPI_R`[src]

Bit 9

`pub fn pads_bank0(&self) -> PADS_BANK0_R`[src]

Bit 8

`pub fn jtag(&self) -> JTAG_R`[src]

Bit 7

`pub fn io_qspi(&self) -> IO_QSPI_R`[src]

Bit 6

`pub fn io_bank0(&self) -> IO_BANK0_R`[src]

Bit 5

`pub fn i2c1(&self) -> I2C1_R`[src]

Bit 4

`pub fn i2c0(&self) -> I2C0_R`[src]

Bit 3

`pub fn dma(&self) -> DMA_R`[src]

Bit 2

`pub fn busctrl(&self) -> BUSCTRL_R`[src]

Bit 1

`pub fn adc(&self) -> ADC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _RESET_DONE>>`[src]

`pub fn usbctrl(&self) -> USBCTRL_R`[src]

Bit 24

`pub fn uart1(&self) -> UART1_R`[src]

Bit 23

`pub fn uart0(&self) -> UART0_R`[src]

Bit 22

`pub fn timer(&self) -> TIMER_R`[src]

Bit 21

`pub fn tbman(&self) -> TBMAN_R`[src]

Bit 20

`pub fn sysinfo(&self) -> SYSINFO_R`[src]

Bit 19

`pub fn syscfg(&self) -> SYSCFG_R`[src]

Bit 18

`pub fn spi1(&self) -> SPI1_R`[src]

Bit 17

`pub fn spi0(&self) -> SPI0_R`[src]

Bit 16

`pub fn rtc(&self) -> RTC_R`[src]

Bit 15

`pub fn pwm(&self) -> PWM_R`[src]

Bit 14

`pub fn pll_usb(&self) -> PLL_USB_R`[src]

Bit 13

`pub fn pll_sys(&self) -> PLL_SYS_R`[src]

Bit 12

`pub fn pio1(&self) -> PIO1_R`[src]

Bit 11

`pub fn pio0(&self) -> PIO0_R`[src]

Bit 10

`pub fn pads_qspi(&self) -> PADS_QSPI_R`[src]

Bit 9

`pub fn pads_bank0(&self) -> PADS_BANK0_R`[src]

Bit 8

`pub fn jtag(&self) -> JTAG_R`[src]

Bit 7

`pub fn io_qspi(&self) -> IO_QSPI_R`[src]

Bit 6

`pub fn io_bank0(&self) -> IO_BANK0_R`[src]

Bit 5

`pub fn i2c1(&self) -> I2C1_R`[src]

Bit 4

`pub fn i2c0(&self) -> I2C0_R`[src]

Bit 3

`pub fn dma(&self) -> DMA_R`[src]

Bit 2

`pub fn busctrl(&self) -> BUSCTRL_R`[src]

Bit 1

`pub fn adc(&self) -> ADC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FRCE_ON>>`[src]

`pub fn proc1(&self) -> PROC1_R`[src]

Bit 16

`pub fn proc0(&self) -> PROC0_R`[src]

Bit 15

`pub fn sio(&self) -> SIO_R`[src]

Bit 14

`pub fn vreg_and_chip_reset(&self) -> VREG_AND_CHIP_RESET_R`[src]

Bit 13

`pub fn xip(&self) -> XIP_R`[src]

Bit 12

`pub fn sram5(&self) -> SRAM5_R`[src]

Bit 11

`pub fn sram4(&self) -> SRAM4_R`[src]

Bit 10

`pub fn sram3(&self) -> SRAM3_R`[src]

Bit 9

`pub fn sram2(&self) -> SRAM2_R`[src]

Bit 8

`pub fn sram1(&self) -> SRAM1_R`[src]

Bit 7

`pub fn sram0(&self) -> SRAM0_R`[src]

Bit 6

`pub fn rom(&self) -> ROM_R`[src]

Bit 5

`pub fn busfabric(&self) -> BUSFABRIC_R`[src]

Bit 4

`pub fn resets(&self) -> RESETS_R`[src]

Bit 3

`pub fn clocks(&self) -> CLOCKS_R`[src]

Bit 2

`pub fn xosc(&self) -> XOSC_R`[src]

Bit 1

`pub fn rosc(&self) -> ROSC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FRCE_OFF>>`[src]

`pub fn proc1(&self) -> PROC1_R`[src]

Bit 16

`pub fn proc0(&self) -> PROC0_R`[src]

Bit 15

`pub fn sio(&self) -> SIO_R`[src]

Bit 14

`pub fn vreg_and_chip_reset(&self) -> VREG_AND_CHIP_RESET_R`[src]

Bit 13

`pub fn xip(&self) -> XIP_R`[src]

Bit 12

`pub fn sram5(&self) -> SRAM5_R`[src]

Bit 11

`pub fn sram4(&self) -> SRAM4_R`[src]

Bit 10

`pub fn sram3(&self) -> SRAM3_R`[src]

Bit 9

`pub fn sram2(&self) -> SRAM2_R`[src]

Bit 8

`pub fn sram1(&self) -> SRAM1_R`[src]

Bit 7

`pub fn sram0(&self) -> SRAM0_R`[src]

Bit 6

`pub fn rom(&self) -> ROM_R`[src]

Bit 5

`pub fn busfabric(&self) -> BUSFABRIC_R`[src]

Bit 4

`pub fn resets(&self) -> RESETS_R`[src]

Bit 3

`pub fn clocks(&self) -> CLOCKS_R`[src]

Bit 2

`pub fn xosc(&self) -> XOSC_R`[src]

Bit 1

`pub fn rosc(&self) -> ROSC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _WDSEL>>`[src]

`pub fn proc1(&self) -> PROC1_R`[src]

Bit 16

`pub fn proc0(&self) -> PROC0_R`[src]

Bit 15

`pub fn sio(&self) -> SIO_R`[src]

Bit 14

`pub fn vreg_and_chip_reset(&self) -> VREG_AND_CHIP_RESET_R`[src]

Bit 13

`pub fn xip(&self) -> XIP_R`[src]

Bit 12

`pub fn sram5(&self) -> SRAM5_R`[src]

Bit 11

`pub fn sram4(&self) -> SRAM4_R`[src]

Bit 10

`pub fn sram3(&self) -> SRAM3_R`[src]

Bit 9

`pub fn sram2(&self) -> SRAM2_R`[src]

Bit 8

`pub fn sram1(&self) -> SRAM1_R`[src]

Bit 7

`pub fn sram0(&self) -> SRAM0_R`[src]

Bit 6

`pub fn rom(&self) -> ROM_R`[src]

Bit 5

`pub fn busfabric(&self) -> BUSFABRIC_R`[src]

Bit 4

`pub fn resets(&self) -> RESETS_R`[src]

Bit 3

`pub fn clocks(&self) -> CLOCKS_R`[src]

Bit 2

`pub fn xosc(&self) -> XOSC_R`[src]

Bit 1

`pub fn rosc(&self) -> ROSC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DONE>>`[src]

`pub fn proc1(&self) -> PROC1_R`[src]

Bit 16

`pub fn proc0(&self) -> PROC0_R`[src]

Bit 15

`pub fn sio(&self) -> SIO_R`[src]

Bit 14

`pub fn vreg_and_chip_reset(&self) -> VREG_AND_CHIP_RESET_R`[src]

Bit 13

`pub fn xip(&self) -> XIP_R`[src]

Bit 12

`pub fn sram5(&self) -> SRAM5_R`[src]

Bit 11

`pub fn sram4(&self) -> SRAM4_R`[src]

Bit 10

`pub fn sram3(&self) -> SRAM3_R`[src]

Bit 9

`pub fn sram2(&self) -> SRAM2_R`[src]

Bit 8

`pub fn sram1(&self) -> SRAM1_R`[src]

Bit 7

`pub fn sram0(&self) -> SRAM0_R`[src]

Bit 6

`pub fn rom(&self) -> ROM_R`[src]

Bit 5

`pub fn busfabric(&self) -> BUSFABRIC_R`[src]

Bit 4

`pub fn resets(&self) -> RESETS_R`[src]

Bit 3

`pub fn clocks(&self) -> CLOCKS_R`[src]

Bit 2

`pub fn xosc(&self) -> XOSC_R`[src]

Bit 1

`pub fn rosc(&self) -> ROSC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _GPIO0_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_jtag_tck(&self) -> bool`[src]

Checks if the value of the field is JTAG_TCK

`pub fn is_spi0_rx(&self) -> bool`[src]

Checks if the value of the field is SPI0_RX

`pub fn is_uart0_tx(&self) -> bool`[src]

Checks if the value of the field is UART0_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_0(&self) -> bool`[src]

Checks if the value of the field is PWM_A_0

`pub fn is_sio_0(&self) -> bool`[src]

Checks if the value of the field is SIO_0

`pub fn is_pio0_0(&self) -> bool`[src]

Checks if the value of the field is PIO0_0

`pub fn is_pio1_0(&self) -> bool`[src]

Checks if the value of the field is PIO1_0

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO0_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO1_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_spi0_ss_n(&self) -> bool`[src]

Checks if the value of the field is SPI0_SS_N

`pub fn is_uart0_rx(&self) -> bool`[src]

Checks if the value of the field is UART0_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_0(&self) -> bool`[src]

Checks if the value of the field is PWM_B_0

`pub fn is_sio_1(&self) -> bool`[src]

Checks if the value of the field is SIO_1

`pub fn is_pio0_1(&self) -> bool`[src]

Checks if the value of the field is PIO0_1

`pub fn is_pio1_1(&self) -> bool`[src]

Checks if the value of the field is PIO1_1

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO1_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO2_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_spi0_sclk(&self) -> bool`[src]

Checks if the value of the field is SPI0_SCLK

`pub fn is_uart0_cts(&self) -> bool`[src]

Checks if the value of the field is UART0_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_1(&self) -> bool`[src]

Checks if the value of the field is PWM_A_1

`pub fn is_sio_2(&self) -> bool`[src]

Checks if the value of the field is SIO_2

`pub fn is_pio0_2(&self) -> bool`[src]

Checks if the value of the field is PIO0_2

`pub fn is_pio1_2(&self) -> bool`[src]

Checks if the value of the field is PIO1_2

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO2_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO3_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_spi0_tx(&self) -> bool`[src]

Checks if the value of the field is SPI0_TX

`pub fn is_uart0_rts(&self) -> bool`[src]

Checks if the value of the field is UART0_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_1(&self) -> bool`[src]

Checks if the value of the field is PWM_B_1

`pub fn is_sio_3(&self) -> bool`[src]

Checks if the value of the field is SIO_3

`pub fn is_pio0_3(&self) -> bool`[src]

Checks if the value of the field is PIO0_3

`pub fn is_pio1_3(&self) -> bool`[src]

Checks if the value of the field is PIO1_3

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO3_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO4_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_tx(&self) -> bool`[src]

Checks if the value of the field is UART1_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_2(&self) -> bool`[src]

Checks if the value of the field is PWM_A_2

`pub fn is_sio_4(&self) -> bool`[src]

Checks if the value of the field is SIO_4

`pub fn is_pio0_4(&self) -> bool`[src]

Checks if the value of the field is PIO0_4

`pub fn is_pio1_4(&self) -> bool`[src]

Checks if the value of the field is PIO1_4

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO4_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO5_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rx(&self) -> bool`[src]

Checks if the value of the field is UART1_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_2(&self) -> bool`[src]

Checks if the value of the field is PWM_B_2

`pub fn is_sio_5(&self) -> bool`[src]

Checks if the value of the field is SIO_5

`pub fn is_pio0_5(&self) -> bool`[src]

Checks if the value of the field is PIO0_5

`pub fn is_pio1_5(&self) -> bool`[src]

Checks if the value of the field is PIO1_5

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO5_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO6_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_cts(&self) -> bool`[src]

Checks if the value of the field is UART1_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_3(&self) -> bool`[src]

Checks if the value of the field is PWM_A_3

`pub fn is_sio_6(&self) -> bool`[src]

Checks if the value of the field is SIO_6

`pub fn is_pio0_6(&self) -> bool`[src]

Checks if the value of the field is PIO0_6

`pub fn is_pio1_6(&self) -> bool`[src]

Checks if the value of the field is PIO1_6

`pub fn is_usb_muxing_extphy_softcon(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_SOFTCON

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO6_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO7_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rts(&self) -> bool`[src]

Checks if the value of the field is UART1_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_3(&self) -> bool`[src]

Checks if the value of the field is PWM_B_3

`pub fn is_sio_7(&self) -> bool`[src]

Checks if the value of the field is SIO_7

`pub fn is_pio0_7(&self) -> bool`[src]

Checks if the value of the field is PIO0_7

`pub fn is_pio1_7(&self) -> bool`[src]

Checks if the value of the field is PIO1_7

`pub fn is_usb_muxing_extphy_oe_n(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_OE_N

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO7_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO8_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_tx(&self) -> bool`[src]

Checks if the value of the field is UART1_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_4(&self) -> bool`[src]

Checks if the value of the field is PWM_A_4

`pub fn is_sio_8(&self) -> bool`[src]

Checks if the value of the field is SIO_8

`pub fn is_pio0_8(&self) -> bool`[src]

Checks if the value of the field is PIO0_8

`pub fn is_pio1_8(&self) -> bool`[src]

Checks if the value of the field is PIO1_8

`pub fn is_usb_muxing_extphy_rcv(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_RCV

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO8_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO9_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rx(&self) -> bool`[src]

Checks if the value of the field is UART1_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_4(&self) -> bool`[src]

Checks if the value of the field is PWM_B_4

`pub fn is_sio_9(&self) -> bool`[src]

Checks if the value of the field is SIO_9

`pub fn is_pio0_9(&self) -> bool`[src]

Checks if the value of the field is PIO0_9

`pub fn is_pio1_9(&self) -> bool`[src]

Checks if the value of the field is PIO1_9

`pub fn is_usb_muxing_extphy_vp(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_VP

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO9_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO10_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_cts(&self) -> bool`[src]

Checks if the value of the field is UART1_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_5(&self) -> bool`[src]

Checks if the value of the field is PWM_A_5

`pub fn is_sio_10(&self) -> bool`[src]

Checks if the value of the field is SIO_10

`pub fn is_pio0_10(&self) -> bool`[src]

Checks if the value of the field is PIO0_10

`pub fn is_pio1_10(&self) -> bool`[src]

Checks if the value of the field is PIO1_10

`pub fn is_usb_muxing_extphy_vm(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_VM

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO10_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO11_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rts(&self) -> bool`[src]

Checks if the value of the field is UART1_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_5(&self) -> bool`[src]

Checks if the value of the field is PWM_B_5

`pub fn is_sio_11(&self) -> bool`[src]

Checks if the value of the field is SIO_11

`pub fn is_pio0_11(&self) -> bool`[src]

Checks if the value of the field is PIO0_11

`pub fn is_pio1_11(&self) -> bool`[src]

Checks if the value of the field is PIO1_11

`pub fn is_usb_muxing_extphy_suspnd(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_SUSPND

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO11_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO12_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_tx(&self) -> bool`[src]

Checks if the value of the field is UART0_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_6(&self) -> bool`[src]

Checks if the value of the field is PWM_A_6

`pub fn is_sio_12(&self) -> bool`[src]

Checks if the value of the field is SIO_12

`pub fn is_pio0_12(&self) -> bool`[src]

Checks if the value of the field is PIO0_12

`pub fn is_pio1_12(&self) -> bool`[src]

Checks if the value of the field is PIO1_12

`pub fn is_usb_muxing_extphy_speed(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_SPEED

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO12_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO13_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_rx(&self) -> bool`[src]

Checks if the value of the field is UART0_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_6(&self) -> bool`[src]

Checks if the value of the field is PWM_B_6

`pub fn is_sio_13(&self) -> bool`[src]

Checks if the value of the field is SIO_13

`pub fn is_pio0_13(&self) -> bool`[src]

Checks if the value of the field is PIO0_13

`pub fn is_pio1_13(&self) -> bool`[src]

Checks if the value of the field is PIO1_13

`pub fn is_usb_muxing_extphy_vpo(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_VPO

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO13_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO14_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_cts(&self) -> bool`[src]

Checks if the value of the field is UART0_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_7(&self) -> bool`[src]

Checks if the value of the field is PWM_A_7

`pub fn is_sio_14(&self) -> bool`[src]

Checks if the value of the field is SIO_14

`pub fn is_pio0_14(&self) -> bool`[src]

Checks if the value of the field is PIO0_14

`pub fn is_pio1_14(&self) -> bool`[src]

Checks if the value of the field is PIO1_14

`pub fn is_usb_muxing_extphy_vmo(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_EXTPHY_VMO

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO14_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO15_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_rts(&self) -> bool`[src]

Checks if the value of the field is UART0_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_7(&self) -> bool`[src]

Checks if the value of the field is PWM_B_7

`pub fn is_sio_15(&self) -> bool`[src]

Checks if the value of the field is SIO_15

`pub fn is_pio0_15(&self) -> bool`[src]

Checks if the value of the field is PIO0_15

`pub fn is_pio1_15(&self) -> bool`[src]

Checks if the value of the field is PIO1_15

`pub fn is_usb_muxing_digital_dp(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_DIGITAL_DP

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO15_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO16_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_tx(&self) -> bool`[src]

Checks if the value of the field is UART0_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_0(&self) -> bool`[src]

Checks if the value of the field is PWM_A_0

`pub fn is_sio_16(&self) -> bool`[src]

Checks if the value of the field is SIO_16

`pub fn is_pio0_16(&self) -> bool`[src]

Checks if the value of the field is PIO0_16

`pub fn is_pio1_16(&self) -> bool`[src]

Checks if the value of the field is PIO1_16

`pub fn is_usb_muxing_digital_dm(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_DIGITAL_DM

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO16_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO17_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_rx(&self) -> bool`[src]

Checks if the value of the field is UART0_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_0(&self) -> bool`[src]

Checks if the value of the field is PWM_B_0

`pub fn is_sio_17(&self) -> bool`[src]

Checks if the value of the field is SIO_17

`pub fn is_pio0_17(&self) -> bool`[src]

Checks if the value of the field is PIO0_17

`pub fn is_pio1_17(&self) -> bool`[src]

Checks if the value of the field is PIO1_17

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO17_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO18_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_cts(&self) -> bool`[src]

Checks if the value of the field is UART0_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_1(&self) -> bool`[src]

Checks if the value of the field is PWM_A_1

`pub fn is_sio_18(&self) -> bool`[src]

Checks if the value of the field is SIO_18

`pub fn is_pio0_18(&self) -> bool`[src]

Checks if the value of the field is PIO0_18

`pub fn is_pio1_18(&self) -> bool`[src]

Checks if the value of the field is PIO1_18

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO18_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO19_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_rts(&self) -> bool`[src]

Checks if the value of the field is UART0_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_1(&self) -> bool`[src]

Checks if the value of the field is PWM_B_1

`pub fn is_sio_19(&self) -> bool`[src]

Checks if the value of the field is SIO_19

`pub fn is_pio0_19(&self) -> bool`[src]

Checks if the value of the field is PIO0_19

`pub fn is_pio1_19(&self) -> bool`[src]

Checks if the value of the field is PIO1_19

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO19_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO20_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_tx(&self) -> bool`[src]

Checks if the value of the field is UART1_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_2(&self) -> bool`[src]

Checks if the value of the field is PWM_A_2

`pub fn is_sio_20(&self) -> bool`[src]

Checks if the value of the field is SIO_20

`pub fn is_pio0_20(&self) -> bool`[src]

Checks if the value of the field is PIO0_20

`pub fn is_pio1_20(&self) -> bool`[src]

Checks if the value of the field is PIO1_20

`pub fn is_clocks_gpin_0(&self) -> bool`[src]

Checks if the value of the field is CLOCKS_GPIN_0

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO20_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO21_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rx(&self) -> bool`[src]

Checks if the value of the field is UART1_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_2(&self) -> bool`[src]

Checks if the value of the field is PWM_B_2

`pub fn is_sio_21(&self) -> bool`[src]

Checks if the value of the field is SIO_21

`pub fn is_pio0_21(&self) -> bool`[src]

Checks if the value of the field is PIO0_21

`pub fn is_pio1_21(&self) -> bool`[src]

Checks if the value of the field is PIO1_21

`pub fn is_clocks_gpout_0(&self) -> bool`[src]

Checks if the value of the field is CLOCKS_GPOUT_0

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO21_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO22_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_cts(&self) -> bool`[src]

Checks if the value of the field is UART1_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_3(&self) -> bool`[src]

Checks if the value of the field is PWM_A_3

`pub fn is_sio_22(&self) -> bool`[src]

Checks if the value of the field is SIO_22

`pub fn is_pio0_22(&self) -> bool`[src]

Checks if the value of the field is PIO0_22

`pub fn is_pio1_22(&self) -> bool`[src]

Checks if the value of the field is PIO1_22

`pub fn is_clocks_gpin_1(&self) -> bool`[src]

Checks if the value of the field is CLOCKS_GPIN_1

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO22_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO23_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rts(&self) -> bool`[src]

Checks if the value of the field is UART1_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_3(&self) -> bool`[src]

Checks if the value of the field is PWM_B_3

`pub fn is_sio_23(&self) -> bool`[src]

Checks if the value of the field is SIO_23

`pub fn is_pio0_23(&self) -> bool`[src]

Checks if the value of the field is PIO0_23

`pub fn is_pio1_23(&self) -> bool`[src]

Checks if the value of the field is PIO1_23

`pub fn is_clocks_gpout_1(&self) -> bool`[src]

Checks if the value of the field is CLOCKS_GPOUT_1

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO23_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO24_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_tx(&self) -> bool`[src]

Checks if the value of the field is UART1_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_4(&self) -> bool`[src]

Checks if the value of the field is PWM_A_4

`pub fn is_sio_24(&self) -> bool`[src]

Checks if the value of the field is SIO_24

`pub fn is_pio0_24(&self) -> bool`[src]

Checks if the value of the field is PIO0_24

`pub fn is_pio1_24(&self) -> bool`[src]

Checks if the value of the field is PIO1_24

`pub fn is_clocks_gpout_2(&self) -> bool`[src]

Checks if the value of the field is CLOCKS_GPOUT_2

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO24_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO25_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rx(&self) -> bool`[src]

Checks if the value of the field is UART1_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_4(&self) -> bool`[src]

Checks if the value of the field is PWM_B_4

`pub fn is_sio_25(&self) -> bool`[src]

Checks if the value of the field is SIO_25

`pub fn is_pio0_25(&self) -> bool`[src]

Checks if the value of the field is PIO0_25

`pub fn is_pio1_25(&self) -> bool`[src]

Checks if the value of the field is PIO1_25

`pub fn is_clocks_gpout_3(&self) -> bool`[src]

Checks if the value of the field is CLOCKS_GPOUT_3

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO25_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO26_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_cts(&self) -> bool`[src]

Checks if the value of the field is UART1_CTS

`pub fn is_i2c1_sda(&self) -> bool`[src]

Checks if the value of the field is I2C1_SDA

`pub fn is_pwm_a_5(&self) -> bool`[src]

Checks if the value of the field is PWM_A_5

`pub fn is_sio_26(&self) -> bool`[src]

Checks if the value of the field is SIO_26

`pub fn is_pio0_26(&self) -> bool`[src]

Checks if the value of the field is PIO0_26

`pub fn is_pio1_26(&self) -> bool`[src]

Checks if the value of the field is PIO1_26

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO26_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO27_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart1_rts(&self) -> bool`[src]

Checks if the value of the field is UART1_RTS

`pub fn is_i2c1_scl(&self) -> bool`[src]

Checks if the value of the field is I2C1_SCL

`pub fn is_pwm_b_5(&self) -> bool`[src]

Checks if the value of the field is PWM_B_5

`pub fn is_sio_27(&self) -> bool`[src]

Checks if the value of the field is SIO_27

`pub fn is_pio0_27(&self) -> bool`[src]

Checks if the value of the field is PIO0_27

`pub fn is_pio1_27(&self) -> bool`[src]

Checks if the value of the field is PIO1_27

`pub fn is_usb_muxing_overcurr_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_OVERCURR_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO27_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO28_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_tx(&self) -> bool`[src]

Checks if the value of the field is UART0_TX

`pub fn is_i2c0_sda(&self) -> bool`[src]

Checks if the value of the field is I2C0_SDA

`pub fn is_pwm_a_6(&self) -> bool`[src]

Checks if the value of the field is PWM_A_6

`pub fn is_sio_28(&self) -> bool`[src]

Checks if the value of the field is SIO_28

`pub fn is_pio0_28(&self) -> bool`[src]

Checks if the value of the field is PIO0_28

`pub fn is_pio1_28(&self) -> bool`[src]

Checks if the value of the field is PIO1_28

`pub fn is_usb_muxing_vbus_detect(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_DETECT

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO28_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO29_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn is_uart0_rx(&self) -> bool`[src]

Checks if the value of the field is UART0_RX

`pub fn is_i2c0_scl(&self) -> bool`[src]

Checks if the value of the field is I2C0_SCL

`pub fn is_pwm_b_6(&self) -> bool`[src]

Checks if the value of the field is PWM_B_6

`pub fn is_sio_29(&self) -> bool`[src]

Checks if the value of the field is SIO_29

`pub fn is_pio0_29(&self) -> bool`[src]

Checks if the value of the field is PIO0_29

`pub fn is_pio1_29(&self) -> bool`[src]

Checks if the value of the field is PIO1_29

`pub fn is_usb_muxing_vbus_en(&self) -> bool`[src]

Checks if the value of the field is USB_MUXING_VBUS_EN

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO29_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _INTR0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTR1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTR2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTR3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTE0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTE1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTE2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTE3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTF0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTF1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTF2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTF3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTS0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTS1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTS2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTS3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTE0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTE1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTE2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTE3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTF0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTF1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTF2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTF3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTS0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTS1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTS2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTS3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTE0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTE1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTE2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTE3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTF0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTF1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTF2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTF3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTS0>>`[src]

`pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTS1>>`[src]

`pub fn gpio15_edge_high(&self) -> GPIO15_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio15_edge_low(&self) -> GPIO15_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio15_level_high(&self) -> GPIO15_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio15_level_low(&self) -> GPIO15_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio14_edge_high(&self) -> GPIO14_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio14_edge_low(&self) -> GPIO14_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio14_level_high(&self) -> GPIO14_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio14_level_low(&self) -> GPIO14_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio13_edge_high(&self) -> GPIO13_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio13_edge_low(&self) -> GPIO13_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio13_level_high(&self) -> GPIO13_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio13_level_low(&self) -> GPIO13_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio12_edge_high(&self) -> GPIO12_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio12_edge_low(&self) -> GPIO12_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio12_level_high(&self) -> GPIO12_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio12_level_low(&self) -> GPIO12_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio11_edge_high(&self) -> GPIO11_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio11_edge_low(&self) -> GPIO11_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio11_level_high(&self) -> GPIO11_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio11_level_low(&self) -> GPIO11_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio10_edge_high(&self) -> GPIO10_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio10_edge_low(&self) -> GPIO10_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio10_level_high(&self) -> GPIO10_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio10_level_low(&self) -> GPIO10_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio9_edge_high(&self) -> GPIO9_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio9_edge_low(&self) -> GPIO9_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio9_level_high(&self) -> GPIO9_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio9_level_low(&self) -> GPIO9_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio8_edge_high(&self) -> GPIO8_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio8_edge_low(&self) -> GPIO8_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio8_level_high(&self) -> GPIO8_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio8_level_low(&self) -> GPIO8_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTS2>>`[src]

`pub fn gpio23_edge_high(&self) -> GPIO23_EDGE_HIGH_R`[src]

Bit 31

`pub fn gpio23_edge_low(&self) -> GPIO23_EDGE_LOW_R`[src]

Bit 30

`pub fn gpio23_level_high(&self) -> GPIO23_LEVEL_HIGH_R`[src]

Bit 29

`pub fn gpio23_level_low(&self) -> GPIO23_LEVEL_LOW_R`[src]

Bit 28

`pub fn gpio22_edge_high(&self) -> GPIO22_EDGE_HIGH_R`[src]

Bit 27

`pub fn gpio22_edge_low(&self) -> GPIO22_EDGE_LOW_R`[src]

Bit 26

`pub fn gpio22_level_high(&self) -> GPIO22_LEVEL_HIGH_R`[src]

Bit 25

`pub fn gpio22_level_low(&self) -> GPIO22_LEVEL_LOW_R`[src]

Bit 24

`pub fn gpio21_edge_high(&self) -> GPIO21_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio21_edge_low(&self) -> GPIO21_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio21_level_high(&self) -> GPIO21_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio21_level_low(&self) -> GPIO21_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio20_edge_high(&self) -> GPIO20_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio20_edge_low(&self) -> GPIO20_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio20_level_high(&self) -> GPIO20_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio20_level_low(&self) -> GPIO20_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio19_edge_high(&self) -> GPIO19_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio19_edge_low(&self) -> GPIO19_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio19_level_high(&self) -> GPIO19_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio19_level_low(&self) -> GPIO19_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio18_edge_high(&self) -> GPIO18_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio18_edge_low(&self) -> GPIO18_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio18_level_high(&self) -> GPIO18_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio18_level_low(&self) -> GPIO18_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio17_edge_high(&self) -> GPIO17_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio17_edge_low(&self) -> GPIO17_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio17_level_high(&self) -> GPIO17_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio17_level_low(&self) -> GPIO17_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio16_edge_high(&self) -> GPIO16_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio16_edge_low(&self) -> GPIO16_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio16_level_high(&self) -> GPIO16_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio16_level_low(&self) -> GPIO16_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTS3>>`[src]

`pub fn gpio29_edge_high(&self) -> GPIO29_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio29_edge_low(&self) -> GPIO29_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio29_level_high(&self) -> GPIO29_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio29_level_low(&self) -> GPIO29_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio28_edge_high(&self) -> GPIO28_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio28_edge_low(&self) -> GPIO28_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio28_level_high(&self) -> GPIO28_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio28_level_low(&self) -> GPIO28_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio27_edge_high(&self) -> GPIO27_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio27_edge_low(&self) -> GPIO27_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio27_level_high(&self) -> GPIO27_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio27_level_low(&self) -> GPIO27_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio26_edge_high(&self) -> GPIO26_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio26_edge_low(&self) -> GPIO26_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio26_level_high(&self) -> GPIO26_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio26_level_low(&self) -> GPIO26_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio25_edge_high(&self) -> GPIO25_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio25_edge_low(&self) -> GPIO25_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio25_level_high(&self) -> GPIO25_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio25_level_low(&self) -> GPIO25_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio24_edge_high(&self) -> GPIO24_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio24_edge_low(&self) -> GPIO24_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio24_level_high(&self) -> GPIO24_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio24_level_low(&self) -> GPIO24_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _GPIO_QSPI_SCLK_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_xip_sclk(&self) -> bool`[src]

Checks if the value of the field is XIP_SCLK

`pub fn is_sio_30(&self) -> bool`[src]

Checks if the value of the field is SIO_30

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SCLK_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SS_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_xip_ss_n(&self) -> bool`[src]

Checks if the value of the field is XIP_SS_N

`pub fn is_sio_31(&self) -> bool`[src]

Checks if the value of the field is SIO_31

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SS_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD0_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_xip_sd0(&self) -> bool`[src]

Checks if the value of the field is XIP_SD0

`pub fn is_sio_32(&self) -> bool`[src]

Checks if the value of the field is SIO_32

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD0_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD1_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_xip_sd1(&self) -> bool`[src]

Checks if the value of the field is XIP_SD1

`pub fn is_sio_33(&self) -> bool`[src]

Checks if the value of the field is SIO_33

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD1_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD2_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_xip_sd2(&self) -> bool`[src]

Checks if the value of the field is XIP_SD2

`pub fn is_sio_34(&self) -> bool`[src]

Checks if the value of the field is SIO_34

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD2_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD3_STATUS>>`[src]

`pub fn irqtoproc(&self) -> IRQTOPROC_R`[src]

Bit 26 - interrupt to processors, after override is applied

`pub fn irqfrompad(&self) -> IRQFROMPAD_R`[src]

Bit 24 - interrupt from pad before override is applied

`pub fn intoperi(&self) -> INTOPERI_R`[src]

Bit 19 - input signal to peripheral, after override is applied

`pub fn infrompad(&self) -> INFROMPAD_R`[src]

Bit 17 - input signal from pad, before override is applied

`pub fn oetopad(&self) -> OETOPAD_R`[src]

Bit 13 - output enable to pad after register override is applied

`pub fn oefromperi(&self) -> OEFROMPERI_R`[src]

Bit 12 - output enable from selected peripheral, before register override is applied

`pub fn outtopad(&self) -> OUTTOPAD_R`[src]

Bit 9 - output signal to pad after register override is applied

`pub fn outfromperi(&self) -> OUTFROMPERI_R`[src]

Bit 8 - output signal from selected peripheral, before register override is applied

`impl R<u8, IRQOVER_A>`[src]

`pub fn variant(&self) -> IRQOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, INOVER_A>`[src]

`pub fn variant(&self) -> INOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, OEOVER_A>`[src]

`pub fn variant(&self) -> OEOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, OUTOVER_A>`[src]

`pub fn variant(&self) -> OUTOVER_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<u8, FUNCSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FUNCSEL_A>`[src]

Get enumerated values variant

`pub fn is_xip_sd3(&self) -> bool`[src]

Checks if the value of the field is XIP_SD3

`pub fn is_sio_35(&self) -> bool`[src]

Checks if the value of the field is SIO_35

`pub fn is_null(&self) -> bool`[src]

Checks if the value of the field is NULL

`impl R<u32, Reg<u32, _GPIO_QSPI_SD3_CTRL>>`[src]

`pub fn irqover(&self) -> IRQOVER_R`[src]

Bits 28:29

`pub fn inover(&self) -> INOVER_R`[src]

Bits 16:17

`pub fn oeover(&self) -> OEOVER_R`[src]

Bits 12:13

`pub fn outover(&self) -> OUTOVER_R`[src]

Bits 8:9

`pub fn funcsel(&self) -> FUNCSEL_R`[src]

Bits 0:4 - 0-31 -> selects pin function according to the gpio table\n 31 == NULL

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTE>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTF>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC0_INTS>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTE>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTF>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PROC1_INTS>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTE>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTF>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DORMANT_WAKE_INTS>>`[src]

`pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R`[src]

Bit 23

`pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R`[src]

Bit 22

`pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R`[src]

Bit 21

`pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R`[src]

Bit 20

`pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R`[src]

Bit 19

`pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R`[src]

Bit 18

`pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R`[src]

Bit 17

`pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R`[src]

Bit 16

`pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R`[src]

Bit 15

`pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R`[src]

Bit 14

`pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R`[src]

Bit 13

`pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R`[src]

Bit 12

`pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R`[src]

Bit 11

`pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R`[src]

Bit 10

`pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R`[src]

Bit 9

`pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R`[src]

Bit 8

`pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R`[src]

Bit 7

`pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R`[src]

Bit 6

`pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R`[src]

Bit 5

`pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R`[src]

Bit 4

`pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R`[src]

Bit 3

`pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R`[src]

Bit 2

`pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R`[src]

Bit 1

`pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R`[src]

Bit 0

`impl R<bool, VOLTAGE_SELECT_A>`[src]

`pub fn variant(&self) -> VOLTAGE_SELECT_A`[src]

Get enumerated values variant

`pub fn is_3v3(&self) -> bool`[src]

Checks if the value of the field is _3V3

`pub fn is_1v8(&self) -> bool`[src]

Checks if the value of the field is _1V8

`impl R<u32, Reg<u32, _VOLTAGE_SELECT>>`[src]

`pub fn voltage_select(&self) -> VOLTAGE_SELECT_R`[src]

Bit 0

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO0>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO1>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO2>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO3>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO4>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO5>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO6>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO7>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO8>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO9>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO10>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO11>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO12>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO13>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO14>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO15>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO16>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO17>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO18>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO19>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO20>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO21>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO22>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO23>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO24>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO25>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO26>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO27>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO28>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO29>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _SWCLK>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _SWD>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<bool, VOLTAGE_SELECT_A>`[src]

`pub fn variant(&self) -> VOLTAGE_SELECT_A`[src]

Get enumerated values variant

`pub fn is_3v3(&self) -> bool`[src]

Checks if the value of the field is _3V3

`pub fn is_1v8(&self) -> bool`[src]

Checks if the value of the field is _1V8

`impl R<u32, Reg<u32, _VOLTAGE_SELECT>>`[src]

`pub fn voltage_select(&self) -> VOLTAGE_SELECT_R`[src]

Bit 0

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO_QSPI_SCLK>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO_QSPI_SD0>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO_QSPI_SD1>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO_QSPI_SD2>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO_QSPI_SD3>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u8, DRIVE_A>`[src]

`pub fn variant(&self) -> DRIVE_A`[src]

Get enumerated values variant

`pub fn is_2m_a(&self) -> bool`[src]

Checks if the value of the field is _2MA

`pub fn is_4m_a(&self) -> bool`[src]

Checks if the value of the field is _4MA

`pub fn is_8m_a(&self) -> bool`[src]

Checks if the value of the field is _8MA

`pub fn is_12m_a(&self) -> bool`[src]

Checks if the value of the field is _12MA

`impl R<u32, Reg<u32, _GPIO_QSPI_SS>>`[src]

`pub fn od(&self) -> OD_R`[src]

Bit 7 - Output disable. Has priority over output enable from peripherals

`pub fn ie(&self) -> IE_R`[src]

Bit 6 - Input enable

`pub fn drive(&self) -> DRIVE_R`[src]

Bits 4:5 - Drive strength.

`pub fn pue(&self) -> PUE_R`[src]

Bit 3 - Pull up enable

`pub fn pde(&self) -> PDE_R`[src]

Bit 2 - Pull down enable

`pub fn schmitt(&self) -> SCHMITT_R`[src]

Bit 1 - Enable schmitt trigger

`pub fn slewfast(&self) -> SLEWFAST_R`[src]

Bit 0 - Slew rate control. 1 = Fast, 0 = Slow

`impl R<u16, ENABLE_A>`[src]

`pub fn variant(&self) -> Variant<u16, ENABLE_A>`[src]

Get enumerated values variant

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u16, FREQ_RANGE_A>`[src]

`pub fn variant(&self) -> Variant<u16, FREQ_RANGE_A>`[src]

Get enumerated values variant

`pub fn is_1_15mhz(&self) -> bool`[src]

Checks if the value of the field is _1_15MHZ

`pub fn is_reserved_1(&self) -> bool`[src]

Checks if the value of the field is RESERVED_1

`pub fn is_reserved_2(&self) -> bool`[src]

Checks if the value of the field is RESERVED_2

`pub fn is_reserved_3(&self) -> bool`[src]

Checks if the value of the field is RESERVED_3

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&self) -> ENABLE_R`[src]

Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.

`pub fn freq_range(&self) -> FREQ_RANGE_R`[src]

Bits 0:11 - Frequency range. This resets to 0xAA0 and cannot be changed.

`impl R<u8, FREQ_RANGE_A>`[src]

`pub fn variant(&self) -> FREQ_RANGE_A`[src]

Get enumerated values variant

`pub fn is_1_15mhz(&self) -> bool`[src]

Checks if the value of the field is _1_15MHZ

`pub fn is_reserved_1(&self) -> bool`[src]

Checks if the value of the field is RESERVED_1

`pub fn is_reserved_2(&self) -> bool`[src]

Checks if the value of the field is RESERVED_2

`pub fn is_reserved_3(&self) -> bool`[src]

Checks if the value of the field is RESERVED_3

`impl R<u32, Reg<u32, _STATUS>>`[src]

`pub fn stable(&self) -> STABLE_R`[src]

Bit 31 - Oscillator is running and stable

`pub fn badwrite(&self) -> BADWRITE_R`[src]

Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT

`pub fn enabled(&self) -> ENABLED_R`[src]

Bit 12 - Oscillator is enabled but not necessarily running and stable, resets to 0

`pub fn freq_range(&self) -> FREQ_RANGE_R`[src]

Bits 0:1 - The current frequency range setting, always reads 0

`impl R<u32, Reg<u32, _STARTUP>>`[src]

`pub fn x4(&self) -> X4_R`[src]

Bit 20 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly

`pub fn delay(&self) -> DELAY_R`[src]

Bits 0:13 - in multiples of 256*xtal_period

`impl R<u32, Reg<u32, _COUNT>>`[src]

`pub fn count(&self) -> COUNT_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CS>>`[src]

`pub fn lock(&self) -> LOCK_R`[src]

Bit 31 - PLL is locked

`pub fn bypass(&self) -> BYPASS_R`[src]

Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

`pub fn refdiv(&self) -> REFDIV_R`[src]

Bits 0:5 - Divides the PLL input reference clock.\n Behaviour is undefined for div=0.\n PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

`impl R<u32, Reg<u32, _PWR>>`[src]

`pub fn vcopd(&self) -> VCOPD_R`[src]

Bit 5 - PLL VCO powerdown\n To save power set high when PLL output not required or bypass=1.

`pub fn postdivpd(&self) -> POSTDIVPD_R`[src]

Bit 3 - PLL post divider powerdown\n To save power set high when PLL output not required or bypass=1.

`pub fn dsmpd(&self) -> DSMPD_R`[src]

Bit 2 - PLL DSM powerdown\n Nothing is achieved by setting this low.

`pub fn pd(&self) -> PD_R`[src]

Bit 0 - PLL powerdown\n To save power set high when PLL output not required.

`impl R<u32, Reg<u32, _FBDIV_INT>>`[src]

`pub fn fbdiv_int(&self) -> FBDIV_INT_R`[src]

Bits 0:11 - see ctrl reg description for constraints

`impl R<u32, Reg<u32, _PRIM>>`[src]

`pub fn postdiv1(&self) -> POSTDIV1_R`[src]

Bits 16:18 - divide by 1-7

`pub fn postdiv2(&self) -> POSTDIV2_R`[src]

Bits 12:14 - divide by 1-7

`impl R<u32, Reg<u32, _BUS_PRIORITY>>`[src]

`pub fn dma_w(&self) -> DMA_W_R`[src]

Bit 12 - 0 - low priority, 1 - high priority

`pub fn dma_r(&self) -> DMA_R_R`[src]

Bit 8 - 0 - low priority, 1 - high priority

`pub fn proc1(&self) -> PROC1_R`[src]

Bit 4 - 0 - low priority, 1 - high priority

`pub fn proc0(&self) -> PROC0_R`[src]

Bit 0 - 0 - low priority, 1 - high priority

`impl R<u32, Reg<u32, _BUS_PRIORITY_ACK>>`[src]

`pub fn bus_priority_ack(&self) -> BUS_PRIORITY_ACK_R`[src]

Bit 0 - Goes to 1 once all arbiters have registered the new global priority levels.\n Arbiters update their local priority when servicing a new nonsequential access.\n In normal circumstances this will happen almost immediately.

`impl R<u32, Reg<u32, _PERFCTR0>>`[src]

`pub fn perfctr0(&self) -> PERFCTR0_R`[src]

Bits 0:23 - Busfabric saturating performance counter 0\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL0

`impl R<u32, Reg<u32, _PERFSEL0>>`[src]

`pub fn perfsel0(&self) -> PERFSEL0_R`[src]

Bits 0:4 - Select a performance event for PERFCTR0

`impl R<u32, Reg<u32, _PERFCTR1>>`[src]

`pub fn perfctr1(&self) -> PERFCTR1_R`[src]

Bits 0:23 - Busfabric saturating performance counter 1\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL1

`impl R<u32, Reg<u32, _PERFSEL1>>`[src]

`pub fn perfsel1(&self) -> PERFSEL1_R`[src]

Bits 0:4 - Select a performance event for PERFCTR1

`impl R<u32, Reg<u32, _PERFCTR2>>`[src]

`pub fn perfctr2(&self) -> PERFCTR2_R`[src]

Bits 0:23 - Busfabric saturating performance counter 2\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL2

`impl R<u32, Reg<u32, _PERFSEL2>>`[src]

`pub fn perfsel2(&self) -> PERFSEL2_R`[src]

Bits 0:4 - Select a performance event for PERFCTR2

`impl R<u32, Reg<u32, _PERFCTR3>>`[src]

`pub fn perfctr3(&self) -> PERFCTR3_R`[src]

Bits 0:23 - Busfabric saturating performance counter 3\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL3

`impl R<u32, Reg<u32, _PERFSEL3>>`[src]

`pub fn perfsel3(&self) -> PERFSEL3_R`[src]

Bits 0:4 - Select a performance event for PERFCTR3

`impl R<u32, Reg<u32, _UARTDR>>`[src]

`pub fn oe(&self) -> OE_R`[src]

Bit 11 - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.

`pub fn be(&self) -> BE_R`[src]

Bit 10 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.

`pub fn pe(&self) -> PE_R`[src]

Bit 9 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.

`pub fn fe(&self) -> FE_R`[src]

Bit 8 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.

`pub fn data(&self) -> DATA_R`[src]

Bits 0:7 - Receive (read) data character. Transmit (write) data character.

`impl R<u32, Reg<u32, _UARTRSR>>`[src]

`pub fn oe(&self) -> OE_R`[src]

Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

`pub fn be(&self) -> BE_R`[src]

Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

`pub fn pe(&self) -> PE_R`[src]

Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

`pub fn fe(&self) -> FE_R`[src]

Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

`impl R<u32, Reg<u32, _UARTFR>>`[src]

`pub fn ri(&self) -> RI_R`[src]

Bit 8 - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.

`pub fn rxff(&self) -> RXFF_R`[src]

Bit 6 - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.

`pub fn txff(&self) -> TXFF_R`[src]

Bit 5 - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.

`pub fn rxfe(&self) -> RXFE_R`[src]

Bit 4 - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.

`pub fn busy(&self) -> BUSY_R`[src]

Bit 3 - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.

`pub fn dcd(&self) -> DCD_R`[src]

Bit 2 - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.

`pub fn dsr(&self) -> DSR_R`[src]

Bit 1 - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.

`pub fn cts(&self) -> CTS_R`[src]

Bit 0 - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.

`impl R<u32, Reg<u32, _UARTILPR>>`[src]

`pub fn ilpdvsr(&self) -> ILPDVSR_R`[src]

Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset.

`impl R<u32, Reg<u32, _UARTIBRD>>`[src]

`pub fn baud_divint(&self) -> BAUD_DIVINT_R`[src]

Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset.

`impl R<u32, Reg<u32, _UARTFBRD>>`[src]

`pub fn baud_divfrac(&self) -> BAUD_DIVFRAC_R`[src]

Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset.

`impl R<u32, Reg<u32, _UARTLCR_H>>`[src]

`pub fn sps(&self) -> SPS_R`[src]

Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

`pub fn wlen(&self) -> WLEN_R`[src]

Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.

`pub fn fen(&self) -> FEN_R`[src]

Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

`pub fn stp2(&self) -> STP2_R`[src]

Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

`pub fn eps(&self) -> EPS_R`[src]

Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

`pub fn pen(&self) -> PEN_R`[src]

Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

`pub fn brk(&self) -> BRK_R`[src]

Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

`impl R<u32, Reg<u32, _UARTCR>>`[src]

`pub fn ctsen(&self) -> CTSEN_R`[src]

Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.

`pub fn rtsen(&self) -> RTSEN_R`[src]

Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.

`pub fn out2(&self) -> OUT2_R`[src]

Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).

`pub fn out1(&self) -> OUT1_R`[src]

Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).

`pub fn rts(&self) -> RTS_R`[src]

Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.

`pub fn dtr(&self) -> DTR_R`[src]

Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.

`pub fn rxe(&self) -> RXE_R`[src]

Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.

`pub fn txe(&self) -> TXE_R`[src]

Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.

`pub fn lbe(&self) -> LBE_R`[src]

Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.

`pub fn sirlp(&self) -> SIRLP_R`[src]

Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.

`pub fn siren(&self) -> SIREN_R`[src]

Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.

`pub fn uarten(&self) -> UARTEN_R`[src]

Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.

`impl R<u32, Reg<u32, _UARTIFLS>>`[src]

`pub fn rxiflsel(&self) -> RXIFLSEL_R`[src]

Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.

`pub fn txiflsel(&self) -> TXIFLSEL_R`[src]

Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.

`impl R<u32, Reg<u32, _UARTIMSC>>`[src]

`pub fn oeim(&self) -> OEIM_R`[src]

Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.

`pub fn beim(&self) -> BEIM_R`[src]

Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.

`pub fn peim(&self) -> PEIM_R`[src]

Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.

`pub fn feim(&self) -> FEIM_R`[src]

Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.

`pub fn rtim(&self) -> RTIM_R`[src]

Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.

`pub fn txim(&self) -> TXIM_R`[src]

Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.

`pub fn rxim(&self) -> RXIM_R`[src]

Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.

`pub fn dsrmim(&self) -> DSRMIM_R`[src]

Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.

`pub fn dcdmim(&self) -> DCDMIM_R`[src]

Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.

`pub fn ctsmim(&self) -> CTSMIM_R`[src]

Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.

`pub fn rimim(&self) -> RIMIM_R`[src]

Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

`impl R<u32, Reg<u32, _UARTRIS>>`[src]

`pub fn oeris(&self) -> OERIS_R`[src]

Bit 10 - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.

`pub fn beris(&self) -> BERIS_R`[src]

Bit 9 - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.

`pub fn peris(&self) -> PERIS_R`[src]

Bit 8 - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.

`pub fn feris(&self) -> FERIS_R`[src]

Bit 7 - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.

`pub fn rtris(&self) -> RTRIS_R`[src]

Bit 6 - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a

`pub fn txris(&self) -> TXRIS_R`[src]

Bit 5 - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.

`pub fn rxris(&self) -> RXRIS_R`[src]

Bit 4 - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.

`pub fn dsrrmis(&self) -> DSRRMIS_R`[src]

Bit 3 - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.

`pub fn dcdrmis(&self) -> DCDRMIS_R`[src]

Bit 2 - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.

`pub fn ctsrmis(&self) -> CTSRMIS_R`[src]

Bit 1 - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.

`pub fn rirmis(&self) -> RIRMIS_R`[src]

Bit 0 - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.

`impl R<u32, Reg<u32, _UARTMIS>>`[src]

`pub fn oemis(&self) -> OEMIS_R`[src]

Bit 10 - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.

`pub fn bemis(&self) -> BEMIS_R`[src]

Bit 9 - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.

`pub fn pemis(&self) -> PEMIS_R`[src]

Bit 8 - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.

`pub fn femis(&self) -> FEMIS_R`[src]

Bit 7 - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.

`pub fn rtmis(&self) -> RTMIS_R`[src]

Bit 6 - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.

`pub fn txmis(&self) -> TXMIS_R`[src]

Bit 5 - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.

`pub fn rxmis(&self) -> RXMIS_R`[src]

Bit 4 - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.

`pub fn dsrmmis(&self) -> DSRMMIS_R`[src]

Bit 3 - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.

`pub fn dcdmmis(&self) -> DCDMMIS_R`[src]

Bit 2 - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.

`pub fn ctsmmis(&self) -> CTSMMIS_R`[src]

Bit 1 - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.

`pub fn rimmis(&self) -> RIMMIS_R`[src]

Bit 0 - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.

`impl R<u32, Reg<u32, _UARTICR>>`[src]

`pub fn oeic(&self) -> OEIC_R`[src]

Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

`pub fn beic(&self) -> BEIC_R`[src]

Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt.

`pub fn peic(&self) -> PEIC_R`[src]

Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt.

`pub fn feic(&self) -> FEIC_R`[src]

Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt.

`pub fn rtic(&self) -> RTIC_R`[src]

Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

`pub fn txic(&self) -> TXIC_R`[src]

Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt.

`pub fn rxic(&self) -> RXIC_R`[src]

Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt.

`pub fn dsrmic(&self) -> DSRMIC_R`[src]

Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

`pub fn dcdmic(&self) -> DCDMIC_R`[src]

Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

`pub fn ctsmic(&self) -> CTSMIC_R`[src]

Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

`pub fn rimic(&self) -> RIMIC_R`[src]

Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

`impl R<u32, Reg<u32, _UARTDMACR>>`[src]

`pub fn dmaonerr(&self) -> DMAONERR_R`[src]

Bit 2 - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

`pub fn txdmae(&self) -> TXDMAE_R`[src]

Bit 1 - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

`pub fn rxdmae(&self) -> RXDMAE_R`[src]

Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

`impl R<u32, Reg<u32, _UARTPERIPHID0>>`[src]

`pub fn partnumber0(&self) -> PARTNUMBER0_R`[src]

Bits 0:7 - These bits read back as 0x11

`impl R<u32, Reg<u32, _UARTPERIPHID1>>`[src]

`pub fn designer0(&self) -> DESIGNER0_R`[src]

Bits 4:7 - These bits read back as 0x1

`pub fn partnumber1(&self) -> PARTNUMBER1_R`[src]

Bits 0:3 - These bits read back as 0x0

`impl R<u32, Reg<u32, _UARTPERIPHID2>>`[src]

`pub fn revision(&self) -> REVISION_R`[src]

Bits 4:7 - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3

`pub fn designer1(&self) -> DESIGNER1_R`[src]

Bits 0:3 - These bits read back as 0x4

`impl R<u32, Reg<u32, _UARTPERIPHID3>>`[src]

`pub fn configuration(&self) -> CONFIGURATION_R`[src]

Bits 0:7 - These bits read back as 0x00

`impl R<u32, Reg<u32, _UARTPCELLID0>>`[src]

`pub fn uartpcellid0(&self) -> UARTPCELLID0_R`[src]

Bits 0:7 - These bits read back as 0x0D

`impl R<u32, Reg<u32, _UARTPCELLID1>>`[src]

`pub fn uartpcellid1(&self) -> UARTPCELLID1_R`[src]

Bits 0:7 - These bits read back as 0xF0

`impl R<u32, Reg<u32, _UARTPCELLID2>>`[src]

`pub fn uartpcellid2(&self) -> UARTPCELLID2_R`[src]

Bits 0:7 - These bits read back as 0x05

`impl R<u32, Reg<u32, _UARTPCELLID3>>`[src]

`pub fn uartpcellid3(&self) -> UARTPCELLID3_R`[src]

Bits 0:7 - These bits read back as 0xB1

`impl R<u32, Reg<u32, _SSPCR0>>`[src]

`pub fn scr(&self) -> SCR_R`[src]

Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.

`pub fn sph(&self) -> SPH_R`[src]

Bit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

`pub fn spo(&self) -> SPO_R`[src]

Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

`pub fn frf(&self) -> FRF_R`[src]

Bits 4:5 - Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.

`pub fn dss(&self) -> DSS_R`[src]

Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.

`impl R<u32, Reg<u32, _SSPCR1>>`[src]

`pub fn sod(&self) -> SOD_R`[src]

Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.

`pub fn ms(&self) -> MS_R`[src]

Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

`pub fn sse(&self) -> SSE_R`[src]

Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

`pub fn lbm(&self) -> LBM_R`[src]

Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

`impl R<u32, Reg<u32, _SSPDR>>`[src]

`pub fn data(&self) -> DATA_R`[src]

Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.

`impl R<u32, Reg<u32, _SSPSR>>`[src]

`pub fn bsy(&self) -> BSY_R`[src]

Bit 4 - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.

`pub fn rff(&self) -> RFF_R`[src]

Bit 3 - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.

`pub fn rne(&self) -> RNE_R`[src]

Bit 2 - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.

`pub fn tnf(&self) -> TNF_R`[src]

Bit 1 - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.

`pub fn tfe(&self) -> TFE_R`[src]

Bit 0 - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.

`impl R<u32, Reg<u32, _SSPCPSR>>`[src]

`pub fn cpsdvsr(&self) -> CPSDVSR_R`[src]

Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.

`impl R<u32, Reg<u32, _SSPIMSC>>`[src]

`pub fn txim(&self) -> TXIM_R`[src]

Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.

`pub fn rxim(&self) -> RXIM_R`[src]

Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.

`pub fn rtim(&self) -> RTIM_R`[src]

Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

`pub fn rorim(&self) -> RORIM_R`[src]

Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.

`impl R<u32, Reg<u32, _SSPRIS>>`[src]

`pub fn txris(&self) -> TXRIS_R`[src]

Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt

`pub fn rxris(&self) -> RXRIS_R`[src]

Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt

`pub fn rtris(&self) -> RTRIS_R`[src]

Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt

`pub fn rorris(&self) -> RORRIS_R`[src]

Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt

`impl R<u32, Reg<u32, _SSPMIS>>`[src]

`pub fn txmis(&self) -> TXMIS_R`[src]

Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt

`pub fn rxmis(&self) -> RXMIS_R`[src]

Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt

`pub fn rtmis(&self) -> RTMIS_R`[src]

Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt

`pub fn rormis(&self) -> RORMIS_R`[src]

Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt

`impl R<u32, Reg<u32, _SSPICR>>`[src]

`pub fn rtic(&self) -> RTIC_R`[src]

Bit 1 - Clears the SSPRTINTR interrupt

`pub fn roric(&self) -> RORIC_R`[src]

Bit 0 - Clears the SSPRORINTR interrupt

`impl R<u32, Reg<u32, _SSPDMACR>>`[src]

`pub fn txdmae(&self) -> TXDMAE_R`[src]

Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

`pub fn rxdmae(&self) -> RXDMAE_R`[src]

Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

`impl R<u32, Reg<u32, _SSPPERIPHID0>>`[src]

`pub fn partnumber0(&self) -> PARTNUMBER0_R`[src]

Bits 0:7 - These bits read back as 0x22

`impl R<u32, Reg<u32, _SSPPERIPHID1>>`[src]

`pub fn designer0(&self) -> DESIGNER0_R`[src]

Bits 4:7 - These bits read back as 0x1

`pub fn partnumber1(&self) -> PARTNUMBER1_R`[src]

Bits 0:3 - These bits read back as 0x0

`impl R<u32, Reg<u32, _SSPPERIPHID2>>`[src]

`pub fn revision(&self) -> REVISION_R`[src]

Bits 4:7 - These bits return the peripheral revision

`pub fn designer1(&self) -> DESIGNER1_R`[src]

Bits 0:3 - These bits read back as 0x4

`impl R<u32, Reg<u32, _SSPPERIPHID3>>`[src]

`pub fn configuration(&self) -> CONFIGURATION_R`[src]

Bits 0:7 - These bits read back as 0x00

`impl R<u32, Reg<u32, _SSPPCELLID0>>`[src]

`pub fn ssppcellid0(&self) -> SSPPCELLID0_R`[src]

Bits 0:7 - These bits read back as 0x0D

`impl R<u32, Reg<u32, _SSPPCELLID1>>`[src]

`pub fn ssppcellid1(&self) -> SSPPCELLID1_R`[src]

Bits 0:7 - These bits read back as 0xF0

`impl R<u32, Reg<u32, _SSPPCELLID2>>`[src]

`pub fn ssppcellid2(&self) -> SSPPCELLID2_R`[src]

Bits 0:7 - These bits read back as 0x05

Checks if the value of the field is STANDARD

`pub fn is_fast(&self) -> bool`[src]

Checks if the value of the field is FAST

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`impl R<bool, MASTER_MODE_A>`[src]

`pub fn variant(&self) -> MASTER_MODE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _IC_CON>>`[src]

`pub fn stop_det_if_master_active(&self) -> STOP_DET_IF_MASTER_ACTIVE_R`[src]

Bit 10 - Master issues the STOP_DET interrupt irrespective of whether master is active or not

`pub fn rx_fifo_full_hld_ctrl(&self) -> RX_FIFO_FULL_HLD_CTRL_R`[src]

Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n Reset value: 0x0.

`pub fn tx_empty_ctrl(&self) -> TX_EMPTY_CTRL_R`[src]

Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0.

`pub fn stop_det_ifaddressed(&self) -> STOP_DET_IFADDRESSED_R`[src]

Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).

`pub fn ic_slave_disable(&self) -> IC_SLAVE_DISABLE_R`[src]

Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.

`pub fn ic_restart_en(&self) -> IC_RESTART_EN_R`[src]

Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n Reset value: ENABLED

`pub fn ic_10bitaddr_master(&self) -> IC_10BITADDR_MASTER_R`[src]

Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing

`pub fn ic_10bitaddr_slave(&self) -> IC_10BITADDR_SLAVE_R`[src]

Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.

`pub fn speed(&self) -> SPEED_R`[src]

Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n 1: standard mode (100 kbit/s)\n\n 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n 3: high speed mode (3.4 Mbit/s)\n\n Note: This field is not applicable when IC_ULTRA_FAST_MODE=1

`pub fn master_mode(&self) -> MASTER_MODE_R`[src]

Bit 0 - This bit controls whether the DW_apb_i2c master is enabled.\n\n NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.

`impl R<bool, SPECIAL_A>`[src]

`pub fn variant(&self) -> SPECIAL_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, GC_OR_START_A>`[src]

`pub fn variant(&self) -> GC_OR_START_A`[src]

Get enumerated values variant

`pub fn is_general_call(&self) -> bool`[src]

Checks if the value of the field is GENERAL_CALL

`pub fn is_start_byte(&self) -> bool`[src]

Checks if the value of the field is START_BYTE

`impl R<u32, Reg<u32, _IC_TAR>>`[src]

`pub fn special(&self) -> SPECIAL_R`[src]

Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0

`pub fn gc_or_start(&self) -> GC_OR_START_R`[src]

Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0

`pub fn ic_tar(&self) -> IC_TAR_R`[src]

Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.

`impl R<u32, Reg<u32, _IC_SAR>>`[src]

`pub fn ic_sar(&self) -> IC_SAR_R`[src]

Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values.

`impl R<bool, FIRST_DATA_BYTE_A>`[src]

`pub fn variant(&self) -> FIRST_DATA_BYTE_A`[src]

Get enumerated values variant

`pub fn is_inactive(&self) -> bool`[src]

Checks if the value of the field is INACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, RESTART_A>`[src]

`pub fn variant(&self) -> RESTART_A`[src]

Get enumerated values variant

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<bool, STOP_A>`[src]

`pub fn variant(&self) -> STOP_A`[src]

Get enumerated values variant

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<bool, CMD_A>`[src]

`pub fn variant(&self) -> CMD_A`[src]

Get enumerated values variant

`pub fn is_write(&self) -> bool`[src]

Checks if the value of the field is WRITE

`pub fn is_read(&self) -> bool`[src]

Checks if the value of the field is READ

`impl R<u32, Reg<u32, _IC_DATA_CMD>>`[src]

`pub fn first_data_byte(&self) -> FIRST_DATA_BYTE_R`[src]

Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n Reset value : 0x0\n\n NOTE: In case of APB_DATA_WIDTH=8,\n\n 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.

`pub fn restart(&self) -> RESTART_R`[src]

Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received.\n\n 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n Reset value: 0x0

`pub fn stop(&self) -> STOP_R`[src]

Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received.\n\n - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0

`pub fn cmd(&self) -> CMD_R`[src]

Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n Reset value: 0x0

`pub fn dat(&self) -> DAT_R`[src]

Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_SS_SCL_HCNT>>`[src]

`pub fn ic_ss_scl_hcnt(&self) -> IC_SS_SCL_HCNT_R`[src]

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.

`impl R<u32, Reg<u32, _IC_SS_SCL_LCNT>>`[src]

`pub fn ic_ss_scl_lcnt(&self) -> IC_SS_SCL_LCNT_R`[src]

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.

`impl R<u32, Reg<u32, _IC_FS_SCL_HCNT>>`[src]

`pub fn ic_fs_scl_hcnt(&self) -> IC_FS_SCL_HCNT_R`[src]

Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.

Checks if the value of the field is INACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<u32, Reg<u32, _IC_INTR_STAT>>`[src]

`pub fn r_master_on_hold(&self) -> R_MASTER_ON_HOLD_R`[src]

Bit 13 - See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n Reset value: 0x0

`pub fn r_restart_det(&self) -> R_RESTART_DET_R`[src]

Bit 12 - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n Reset value: 0x0

`pub fn r_gen_call(&self) -> R_GEN_CALL_R`[src]

Bit 11 - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n Reset value: 0x0

`pub fn r_start_det(&self) -> R_START_DET_R`[src]

Bit 10 - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n Reset value: 0x0

`pub fn r_stop_det(&self) -> R_STOP_DET_R`[src]

Bit 9 - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n Reset value: 0x0

`pub fn r_activity(&self) -> R_ACTIVITY_R`[src]

Bit 8 - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n Reset value: 0x0

`pub fn r_rx_done(&self) -> R_RX_DONE_R`[src]

Bit 7 - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n Reset value: 0x0

`pub fn r_tx_abrt(&self) -> R_TX_ABRT_R`[src]

Bit 6 - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n Reset value: 0x0

`pub fn r_rd_req(&self) -> R_RD_REQ_R`[src]

Bit 5 - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n Reset value: 0x0

`pub fn r_tx_empty(&self) -> R_TX_EMPTY_R`[src]

Bit 4 - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n Reset value: 0x0

`pub fn r_tx_over(&self) -> R_TX_OVER_R`[src]

`pub fn m_start_det(&self) -> M_START_DET_R`[src]

Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

`pub fn m_stop_det(&self) -> M_STOP_DET_R`[src]

Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

`pub fn m_activity(&self) -> M_ACTIVITY_R`[src]

Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0

`pub fn m_rx_done(&self) -> M_RX_DONE_R`[src]

Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

`pub fn m_tx_abrt(&self) -> M_TX_ABRT_R`[src]

Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

`pub fn m_rd_req(&self) -> M_RD_REQ_R`[src]

Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

`pub fn m_tx_empty(&self) -> M_TX_EMPTY_R`[src]

Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1

`pub fn m_tx_over(&self) -> M_TX_OVER_R`[src]

`pub fn start_det(&self) -> START_DET_R`[src]

Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n Reset value: 0x0

`pub fn stop_det(&self) -> STOP_DET_R`[src]

Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0

`pub fn activity(&self) -> ACTIVITY_R`[src]

Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n Reset value: 0x0

`pub fn rx_done(&self) -> RX_DONE_R`[src]

Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n Reset value: 0x0

`pub fn tx_abrt(&self) -> TX_ABRT_R`[src]

Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n Reset value: 0x0

`pub fn rd_req(&self) -> RD_REQ_R`[src]

Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n Reset value: 0x0

`pub fn tx_empty(&self) -> TX_EMPTY_R`[src]

Bit 4 - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n Reset value: 0x0.

`pub fn tx_over(&self) -> TX_OVER_R`[src]

Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Reset value: 0x0

`pub fn rx_full(&self) -> RX_FULL_R`[src]

Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n Reset value: 0x0

`pub fn rx_over(&self) -> RX_OVER_R`[src]

Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n Reset value: 0x0

`pub fn rx_under(&self) -> RX_UNDER_R`[src]

Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_RX_TL>>`[src]

`pub fn rx_tl(&self) -> RX_TL_R`[src]

Bits 0:7 - Receive FIFO Threshold Level.\n\n Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.

`impl R<u32, Reg<u32, _IC_TX_TL>>`[src]

`pub fn tx_tl(&self) -> TX_TL_R`[src]

Bits 0:7 - Transmit FIFO Threshold Level.\n\n Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.

`impl R<u32, Reg<u32, _IC_CLR_INTR>>`[src]

`pub fn clr_intr(&self) -> CLR_INTR_R`[src]

Bit 0 - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_RX_UNDER>>`[src]

`pub fn clr_rx_under(&self) -> CLR_RX_UNDER_R`[src]

Bit 0 - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_RX_OVER>>`[src]

`pub fn clr_rx_over(&self) -> CLR_RX_OVER_R`[src]

Bit 0 - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_TX_OVER>>`[src]

`pub fn clr_tx_over(&self) -> CLR_TX_OVER_R`[src]

Bit 0 - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_RD_REQ>>`[src]

`pub fn clr_rd_req(&self) -> CLR_RD_REQ_R`[src]

Bit 0 - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_TX_ABRT>>`[src]

`pub fn clr_tx_abrt(&self) -> CLR_TX_ABRT_R`[src]

Bit 0 - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_RX_DONE>>`[src]

`pub fn clr_rx_done(&self) -> CLR_RX_DONE_R`[src]

Bit 0 - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_ACTIVITY>>`[src]

`pub fn clr_activity(&self) -> CLR_ACTIVITY_R`[src]

Bit 0 - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_STOP_DET>>`[src]

`pub fn clr_stop_det(&self) -> CLR_STOP_DET_R`[src]

Bit 0 - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_CLR_START_DET>>`[src]

`pub fn clr_start_det(&self) -> CLR_START_DET_R`[src]

Bit 0 - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

Bit 5 - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n Reset value: 0x0

`pub fn rff(&self) -> RFF_R`[src]

Bit 4 - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0

`pub fn rfne(&self) -> RFNE_R`[src]

Bit 3 - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0

`pub fn tfe(&self) -> TFE_R`[src]

Bit 2 - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1

`pub fn tfnf(&self) -> TFNF_R`[src]

Bit 1 - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1

`pub fn activity(&self) -> ACTIVITY_R`[src]

Bit 0 - I2C Activity Status. Reset value: 0x0

`impl R<u32, Reg<u32, _IC_TXFLR>>`[src]

`pub fn txflr(&self) -> TXFLR_R`[src]

Bits 0:4 - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_RXFLR>>`[src]

`pub fn rxflr(&self) -> RXFLR_R`[src]

Bits 0:4 - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n Reset value: 0x0

Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter

`pub fn abrt_user_abrt(&self) -> ABRT_USER_ABRT_R`[src]

Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter

`pub fn abrt_slvrd_intx(&self) -> ABRT_SLVRD_INTX_R`[src]

Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter

`pub fn abrt_slv_arblost(&self) -> ABRT_SLV_ARBLOST_R`[src]

Bit 14 - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter

`pub fn abrt_slvflush_txfifo(&self) -> ABRT_SLVFLUSH_TXFIFO_R`[src]

Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter

`pub fn arb_lost(&self) -> ARB_LOST_R`[src]

Bit 12 - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter

`pub fn abrt_master_dis(&self) -> ABRT_MASTER_DIS_R`[src]

Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

`pub fn abrt_10b_rd_norstrt(&self) -> ABRT_10B_RD_NORSTRT_R`[src]

Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Receiver

`pub fn abrt_sbyte_norstrt(&self) -> ABRT_SBYTE_NORSTRT_R`[src]

Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master

`pub fn abrt_hs_norstrt(&self) -> ABRT_HS_NORSTRT_R`[src]

Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

`pub fn abrt_sbyte_ackdet(&self) -> ABRT_SBYTE_ACKDET_R`[src]

Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master

`pub fn abrt_hs_ackdet(&self) -> ABRT_HS_ACKDET_R`[src]

Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master

`pub fn abrt_gcall_read(&self) -> ABRT_GCALL_READ_R`[src]

Bit 5 - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter

`pub fn abrt_gcall_noack(&self) -> ABRT_GCALL_NOACK_R`[src]

Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter

`pub fn abrt_txdata_noack(&self) -> ABRT_TXDATA_NOACK_R`[src]

Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter

`pub fn abrt_10addr2_noack(&self) -> ABRT_10ADDR2_NOACK_R`[src]

Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

`pub fn abrt_10addr1_noack(&self) -> ABRT_10ADDR1_NOACK_R`[src]

Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

`pub fn abrt_7b_addr_noack(&self) -> ABRT_7B_ADDR_NOACK_R`[src]

Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

`impl R<bool, NACK_A>`[src]

`pub fn variant(&self) -> NACK_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _IC_SLV_DATA_NACK_ONLY>>`[src]

`pub fn nack(&self) -> NACK_R`[src]

Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0

`impl R<bool, TDMAE_A>`[src]

`pub fn variant(&self) -> TDMAE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, RDMAE_A>`[src]

`pub fn variant(&self) -> RDMAE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _IC_DMA_CR>>`[src]

`pub fn tdmae(&self) -> TDMAE_R`[src]

Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0

`pub fn rdmae(&self) -> RDMAE_R`[src]

Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0

`impl R<u32, Reg<u32, _IC_DMA_TDLR>>`[src]

`pub fn dmatdl(&self) -> DMATDL_R`[src]

Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_DMA_RDLR>>`[src]

`pub fn dmardl(&self) -> DMARDL_R`[src]

Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_SDA_SETUP>>`[src]

`pub fn sda_setup(&self) -> SDA_SETUP_R`[src]

Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.

`impl R<bool, ACK_GEN_CALL_A>`[src]

`pub fn variant(&self) -> ACK_GEN_CALL_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _IC_ACK_GENERAL_CALL>>`[src]

`pub fn ack_gen_call(&self) -> ACK_GEN_CALL_R`[src]

Bit 0 - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).

`impl R<bool, SLV_RX_DATA_LOST_A>`[src]

`pub fn variant(&self) -> SLV_RX_DATA_LOST_A`[src]

Get enumerated values variant

`pub fn is_inactive(&self) -> bool`[src]

Checks if the value of the field is INACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, SLV_DISABLED_WHILE_BUSY_A>`[src]

`pub fn variant(&self) -> SLV_DISABLED_WHILE_BUSY_A`[src]

Get enumerated values variant

`pub fn is_inactive(&self) -> bool`[src]

Checks if the value of the field is INACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, IC_EN_A>`[src]

`pub fn variant(&self) -> IC_EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _IC_ENABLE_STATUS>>`[src]

`pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R`[src]

Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n Reset value: 0x0

`pub fn slv_disabled_while_busy(&self) -> SLV_DISABLED_WHILE_BUSY_R`[src]

Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n OR,\n\n (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n Reset value: 0x0

`pub fn ic_en(&self) -> IC_EN_R`[src]

Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_FS_SPKLEN>>`[src]

`pub fn ic_fs_spklen(&self) -> IC_FS_SPKLEN_R`[src]

Bits 0:7 - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.

`impl R<u32, Reg<u32, _IC_CLR_RESTART_DET>>`[src]

`pub fn clr_restart_det(&self) -> CLR_RESTART_DET_R`[src]

Bit 0 - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0

`impl R<u32, Reg<u32, _IC_COMP_PARAM_1>>`[src]

`pub fn tx_buffer_depth(&self) -> TX_BUFFER_DEPTH_R`[src]

Bits 16:23 - TX Buffer Depth = 16

`pub fn rx_buffer_depth(&self) -> RX_BUFFER_DEPTH_R`[src]

Bits 8:15 - RX Buffer Depth = 16

`pub fn add_encoded_params(&self) -> ADD_ENCODED_PARAMS_R`[src]

Bit 7 - Encoded parameters not visible

`pub fn has_dma(&self) -> HAS_DMA_R`[src]

Bit 6 - DMA handshaking signals are enabled

`pub fn intr_io(&self) -> INTR_IO_R`[src]

Bit 5 - COMBINED Interrupt outputs

`pub fn hc_count_values(&self) -> HC_COUNT_VALUES_R`[src]

Bit 4 - Programmable count values for each mode.

`pub fn max_speed_mode(&self) -> MAX_SPEED_MODE_R`[src]

Bits 2:3 - MAX SPEED MODE = FAST MODE

`pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R`[src]

Bits 0:1 - APB data bus width is 32 bits

`impl R<u32, Reg<u32, _IC_COMP_VERSION>>`[src]

`pub fn ic_comp_version(&self) -> IC_COMP_VERSION_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _IC_COMP_TYPE>>`[src]

`pub fn ic_comp_type(&self) -> IC_COMP_TYPE_R`[src]

Bits 0:31 - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.

`impl R<u32, Reg<u32, _CS>>`[src]

`pub fn rrobin(&self) -> RROBIN_R`[src]

Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n The first channel to be sampled will be the one currently indicated by AINSEL.\n AINSEL will be updated after each conversion with the newly-selected channel.

`pub fn ainsel(&self) -> AINSEL_R`[src]

Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode.

`pub fn err_sticky(&self) -> ERR_STICKY_R`[src]

Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear.

`pub fn err(&self) -> ERR_R`[src]

Bit 9 - The most recent ADC conversion encountered an error; result is undefined or noisy.

`pub fn ready(&self) -> READY_R`[src]

Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n 0 whilst conversion in progress.

`pub fn start_many(&self) -> START_MANY_R`[src]

Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.

`pub fn start_once(&self) -> START_ONCE_R`[src]

Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted.

`pub fn ts_en(&self) -> TS_EN_R`[src]

Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Power on ADC and enable its clock.\n 1 - enabled. 0 - disabled.

`impl R<u32, Reg<u32, _RESULT>>`[src]

`pub fn result(&self) -> RESULT_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _FCS>>`[src]

`pub fn thresh(&self) -> THRESH_R`[src]

Bits 24:27 - DREQ/IRQ asserted when level >= threshold

`pub fn level(&self) -> LEVEL_R`[src]

Bits 16:19 - The number of conversion results currently waiting in the FIFO

`pub fn over(&self) -> OVER_R`[src]

Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear.

`pub fn under(&self) -> UNDER_R`[src]

Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear.

`pub fn full(&self) -> FULL_R`[src]

Bit 9

`pub fn empty(&self) -> EMPTY_R`[src]

Bit 8

`pub fn dreq_en(&self) -> DREQ_EN_R`[src]

Bit 3 - If 1: assert DMA requests when FIFO contains data

`pub fn err(&self) -> ERR_R`[src]

Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result

`pub fn shift(&self) -> SHIFT_R`[src]

Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - If 1: write result to the FIFO after each conversion.

`impl R<u32, Reg<u32, _FIFO>>`[src]

`pub fn err(&self) -> ERR_R`[src]

Bit 15 - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.

`pub fn val(&self) -> VAL_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _DIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 8:23 - Integer part of clock divisor.

`pub fn frac(&self) -> FRAC_R`[src]

Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma.

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn fifo(&self) -> FIFO_R`[src]

Bit 0 - Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field.

`impl R<u32, Reg<u32, _INTE>>`[src]

`pub fn fifo(&self) -> FIFO_R`[src]

Bit 0 - Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field.

`impl R<u32, Reg<u32, _INTF>>`[src]

`pub fn fifo(&self) -> FIFO_R`[src]

Bit 0 - Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field.

`impl R<u32, Reg<u32, _INTS>>`[src]

`pub fn fifo(&self) -> FIFO_R`[src]

Bit 0 - Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field.

`impl R<u8, DIVMODE_A>`[src]

`pub fn variant(&self) -> DIVMODE_A`[src]

Get enumerated values variant

`pub fn is_div(&self) -> bool`[src]

Checks if the value of the field is DIV

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH0_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH1_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH2_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH3_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH4_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH5_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH6_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn is_level(&self) -> bool`[src]

Checks if the value of the field is LEVEL

`pub fn is_rise(&self) -> bool`[src]

Checks if the value of the field is RISE

`pub fn is_fall(&self) -> bool`[src]

Checks if the value of the field is FALL

`impl R<u32, Reg<u32, _CH7_CSR>>`[src]

`pub fn ph_adv(&self) -> PH_ADV_R`[src]

Bit 7 - Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1)

`pub fn ph_ret(&self) -> PH_RET_R`[src]

Bit 6 - Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running.

`pub fn divmode(&self) -> DIVMODE_R`[src]

Bits 4:5

`pub fn b_inv(&self) -> B_INV_R`[src]

Bit 3 - Invert output B

`pub fn a_inv(&self) -> A_INV_R`[src]

Bit 2 - Invert output A

`pub fn ph_correct(&self) -> PH_CORRECT_R`[src]

`pub fn ch5(&self) -> CH5_R`[src]

Bit 5

`pub fn ch4(&self) -> CH4_R`[src]

Bit 4

`pub fn ch3(&self) -> CH3_R`[src]

Bit 3

`pub fn ch2(&self) -> CH2_R`[src]

Bit 2

`pub fn ch1(&self) -> CH1_R`[src]

Bit 1

`pub fn ch0(&self) -> CH0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn ch7(&self) -> CH7_R`[src]

Bit 7

`pub fn ch6(&self) -> CH6_R`[src]

Bit 6

`pub fn ch5(&self) -> CH5_R`[src]

Bit 5

`pub fn ch4(&self) -> CH4_R`[src]

Bit 4

`pub fn ch3(&self) -> CH3_R`[src]

Bit 3

`pub fn ch2(&self) -> CH2_R`[src]

Bit 2

`pub fn ch1(&self) -> CH1_R`[src]

Bit 1

`pub fn ch0(&self) -> CH0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTE>>`[src]

`pub fn ch7(&self) -> CH7_R`[src]

Bit 7

`pub fn ch6(&self) -> CH6_R`[src]

Bit 6

`pub fn ch5(&self) -> CH5_R`[src]

Bit 5

`pub fn ch4(&self) -> CH4_R`[src]

Bit 4

`pub fn ch3(&self) -> CH3_R`[src]

Bit 3

`pub fn ch2(&self) -> CH2_R`[src]

Bit 2

`pub fn ch1(&self) -> CH1_R`[src]

Bit 1

`pub fn ch0(&self) -> CH0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTF>>`[src]

`pub fn ch7(&self) -> CH7_R`[src]

Bit 7

`pub fn ch6(&self) -> CH6_R`[src]

Bit 6

`pub fn ch5(&self) -> CH5_R`[src]

Bit 5

`pub fn ch4(&self) -> CH4_R`[src]

Bit 4

`pub fn ch3(&self) -> CH3_R`[src]

Bit 3

`pub fn ch2(&self) -> CH2_R`[src]

Bit 2

`pub fn ch1(&self) -> CH1_R`[src]

Bit 1

`pub fn ch0(&self) -> CH0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INTS>>`[src]

`pub fn ch7(&self) -> CH7_R`[src]

Bit 7

`pub fn ch6(&self) -> CH6_R`[src]

Bit 6

`pub fn ch5(&self) -> CH5_R`[src]

Bit 5

`pub fn ch4(&self) -> CH4_R`[src]

Bit 4

`pub fn ch3(&self) -> CH3_R`[src]

Bit 3

`pub fn ch2(&self) -> CH2_R`[src]

Bit 2

`pub fn ch1(&self) -> CH1_R`[src]

Bit 1

`pub fn ch0(&self) -> CH0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ARMED>>`[src]

`pub fn armed(&self) -> ARMED_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _DBGPAUSE>>`[src]

`pub fn dbg1(&self) -> DBG1_R`[src]

Bit 2 - Pause when processor 1 is in debug mode

`pub fn dbg0(&self) -> DBG0_R`[src]

Bit 1 - Pause when processor 0 is in debug mode

Bit 26 - Pause the watchdog timer when processor 1 is in debug mode

`pub fn pause_dbg0(&self) -> PAUSE_DBG0_R`[src]

Bit 25 - Pause the watchdog timer when processor 0 is in debug mode

`pub fn pause_jtag(&self) -> PAUSE_JTAG_R`[src]

Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric

`pub fn time(&self) -> TIME_R`[src]

Bits 0:23 - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered

`impl R<u32, Reg<u32, _REASON>>`[src]

`pub fn force(&self) -> FORCE_R`[src]

Bit 1

`pub fn timer(&self) -> TIMER_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TICK>>`[src]

`pub fn count(&self) -> COUNT_R`[src]

Bits 11:19 - Count down timer: the remaining number clk_tick cycles before the next tick is generated.

`pub fn running(&self) -> RUNNING_R`[src]

Bit 10 - Is the tick generator running?

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 9 - start / stop tick generation

`pub fn cycles(&self) -> CYCLES_R`[src]

Bits 0:8 - Total number of clk_tick cycles before the next tick.

`impl R<u32, Reg<u32, _CLKDIV_M1>>`[src]

`pub fn clkdiv_m1(&self) -> CLKDIV_M1_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SETUP_0>>`[src]

`pub fn year(&self) -> YEAR_R`[src]

Bits 12:23 - Year

`pub fn month(&self) -> MONTH_R`[src]

Bits 8:11 - Month (1..12)

`pub fn day(&self) -> DAY_R`[src]

Bits 0:4 - Day of the month (1..31)

`impl R<u32, Reg<u32, _SETUP_1>>`[src]

`pub fn dotw(&self) -> DOTW_R`[src]

Bits 24:26 - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7

`pub fn hour(&self) -> HOUR_R`[src]

Bits 16:20 - Hours

`pub fn min(&self) -> MIN_R`[src]

Bits 8:13 - Minutes

`pub fn sec(&self) -> SEC_R`[src]

Bits 0:5 - Seconds

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn force_notleapyear(&self) -> FORCE_NOTLEAPYEAR_R`[src]

Bit 8 - If set, leapyear is forced off.\n Useful for years divisible by 100 but not by 400

`pub fn load(&self) -> LOAD_R`[src]

Bit 4 - Load RTC

`pub fn rtc_active(&self) -> RTC_ACTIVE_R`[src]

Bit 1 - RTC enabled (running)

`pub fn rtc_enable(&self) -> RTC_ENABLE_R`[src]

Bit 0 - Enable RTC

`impl R<u32, Reg<u32, _IRQ_SETUP_0>>`[src]

`pub fn match_active(&self) -> MATCH_ACTIVE_R`[src]

Bit 29

`pub fn match_ena(&self) -> MATCH_ENA_R`[src]

Bit 28 - Global match enable. Don't change any other value while this one is enabled

`pub fn year_ena(&self) -> YEAR_ENA_R`[src]

Bit 26 - Enable year matching

`pub fn month_ena(&self) -> MONTH_ENA_R`[src]

Bit 25 - Enable month matching

`pub fn day_ena(&self) -> DAY_ENA_R`[src]

Bit 24 - Enable day matching

`pub fn year(&self) -> YEAR_R`[src]

Bits 12:23 - Year

`pub fn month(&self) -> MONTH_R`[src]

Bits 8:11 - Month (1..12)

`pub fn day(&self) -> DAY_R`[src]

Bits 0:4 - Day of the month (1..31)

`impl R<u32, Reg<u32, _IRQ_SETUP_1>>`[src]

`pub fn dotw_ena(&self) -> DOTW_ENA_R`[src]

Bit 31 - Enable day of the week matching

`pub fn hour_ena(&self) -> HOUR_ENA_R`[src]

Bit 30 - Enable hour matching

`pub fn min_ena(&self) -> MIN_ENA_R`[src]

Bit 29 - Enable minute matching

`pub fn sec_ena(&self) -> SEC_ENA_R`[src]

Bit 28 - Enable second matching

`pub fn dotw(&self) -> DOTW_R`[src]

Bits 24:26 - Day of the week

`pub fn hour(&self) -> HOUR_R`[src]

Bits 16:20 - Hours

`pub fn min(&self) -> MIN_R`[src]

Bits 8:13 - Minutes

`pub fn sec(&self) -> SEC_R`[src]

Bits 0:5 - Seconds

`impl R<u32, Reg<u32, _RTC_1>>`[src]

`pub fn year(&self) -> YEAR_R`[src]

Bits 12:23 - Year

`pub fn month(&self) -> MONTH_R`[src]

Bits 8:11 - Month (1..12)

`pub fn day(&self) -> DAY_R`[src]

Bits 0:4 - Day of the month (1..31)

`impl R<u32, Reg<u32, _RTC_0>>`[src]

`pub fn dotw(&self) -> DOTW_R`[src]

Bits 24:26 - Day of the week

`pub fn hour(&self) -> HOUR_R`[src]

Bits 16:20 - Hours

`pub fn min(&self) -> MIN_R`[src]

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u16, FREQ_RANGE_A>`[src]

`pub fn variant(&self) -> Variant<u16, FREQ_RANGE_A>`[src]

Get enumerated values variant

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_medium(&self) -> bool`[src]

Checks if the value of the field is MEDIUM

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_toohigh(&self) -> bool`[src]

Checks if the value of the field is TOOHIGH

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&self) -> ENABLE_R`[src]

Bits 12:23 - On power-up this field is initialised to ENABLE\n The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.

`pub fn freq_range(&self) -> FREQ_RANGE_R`[src]

Bits 0:11 - Controls the number of delay stages in the ROSC ring\n LOW uses stages 0 to 7\n MEDIUM uses stages 0 to 5\n HIGH uses stages 0 to 3\n TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n The clock output will not glitch when changing the range up one step at a time\n The clock output will glitch when changing the range down\n Note: the values here are gray coded which is why HIGH comes before TOOHIGH

`impl R<u16, PASSWD_A>`[src]

`pub fn variant(&self) -> Variant<u16, PASSWD_A>`[src]

Get enumerated values variant

`pub fn is_pass(&self) -> bool`[src]

Checks if the value of the field is PASS

`impl R<u32, Reg<u32, _FREQA>>`[src]

`pub fn passwd(&self) -> PASSWD_R`[src]

Bits 16:31 - Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0

`pub fn ds3(&self) -> DS3_R`[src]

Bits 12:14 - Stage 3 drive strength

`pub fn ds2(&self) -> DS2_R`[src]

Bits 8:10 - Stage 2 drive strength

`pub fn ds1(&self) -> DS1_R`[src]

Bits 4:6 - Stage 1 drive strength

`pub fn ds0(&self) -> DS0_R`[src]

Bits 0:2 - Stage 0 drive strength

`impl R<u16, PASSWD_A>`[src]

`pub fn variant(&self) -> Variant<u16, PASSWD_A>`[src]

Get enumerated values variant

`pub fn is_pass(&self) -> bool`[src]

Checks if the value of the field is PASS

`impl R<u32, Reg<u32, _FREQB>>`[src]

`pub fn passwd(&self) -> PASSWD_R`[src]

Bits 16:31 - Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0

`pub fn ds7(&self) -> DS7_R`[src]

Bits 12:14 - Stage 7 drive strength

`pub fn ds6(&self) -> DS6_R`[src]

Bits 8:10 - Stage 6 drive strength

`pub fn ds5(&self) -> DS5_R`[src]

Bits 4:6 - Stage 5 drive strength

`pub fn ds4(&self) -> DS4_R`[src]

Bits 0:2 - Stage 4 drive strength

`impl R<u16, DIV_A>`[src]

`pub fn variant(&self) -> Variant<u16, DIV_A>`[src]

Get enumerated values variant

`pub fn is_pass(&self) -> bool`[src]

Checks if the value of the field is PASS

`impl R<u32, Reg<u32, _DIV>>`[src]

`pub fn div(&self) -> DIV_R`[src]

Bits 0:11 - set to 0xaa0 + div where\n div = 0 divides by 32\n div = 1-31 divides by div\n any other value sets div=0 and therefore divides by 32\n this register resets to div=16

`impl R<u32, Reg<u32, _PHASE>>`[src]

`pub fn passwd(&self) -> PASSWD_R`[src]

Bits 4:11 - set to 0xaa0\n any other value enables the output with shift=0

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 3 - enable the phase-shifted output\n this can be changed on-the-fly

`pub fn flip(&self) -> FLIP_R`[src]

Bit 2 - invert the phase-shifted output\n this is ignored when div=1

`pub fn shift(&self) -> SHIFT_R`[src]

Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks\n this can be changed on-the-fly\n must be set to 0 before setting div=1

`impl R<u32, Reg<u32, _STATUS>>`[src]

`pub fn stable(&self) -> STABLE_R`[src]

Bit 31 - Oscillator is running and stable

`pub fn badwrite(&self) -> BADWRITE_R`[src]

Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT

`pub fn div_running(&self) -> DIV_RUNNING_R`[src]

Bit 16 - post-divider is running\n this resets to 0 but transitions to 1 during chip startup

`pub fn enabled(&self) -> ENABLED_R`[src]

Bit 12 - Oscillator is enabled but not necessarily running and stable\n this resets to 0 but transitions to 1 during chip startup

`impl R<u32, Reg<u32, _RANDOMBIT>>`[src]

`pub fn randombit(&self) -> RANDOMBIT_R`[src]

Bit 0

`impl R<u32, Reg<u32, _COUNT>>`[src]

`pub fn count(&self) -> COUNT_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _VREG>>`[src]

`pub fn rok(&self) -> ROK_R`[src]

Bit 12 - regulation status\n 0=not in regulation, 1=in regulation

`pub fn vsel(&self) -> VSEL_R`[src]

Bits 4:7 - output voltage select\n 0000 to 0101 - 0.80V\n 0110 - 0.85V\n 0111 - 0.90V\n 1000 - 0.95V\n 1001 - 1.00V\n 1010 - 1.05V\n 1011 - 1.10V (default)\n 1100 - 1.15V\n 1101 - 1.20V\n 1110 - 1.25V\n 1111 - 1.30V

`pub fn hiz(&self) -> HIZ_R`[src]

Bit 1 - high impedance mode select\n 0=not in high impedance mode, 1=in high impedance mode

`pub fn en(&self) -> EN_R`[src]

Bit 0 - enable\n 0=not enabled, 1=enabled

`impl R<u32, Reg<u32, _BOD>>`[src]

`pub fn vsel(&self) -> VSEL_R`[src]

Bits 4:7 - threshold select\n 0000 - 0.473V\n 0001 - 0.516V\n 0010 - 0.559V\n 0011 - 0.602V\n 0100 - 0.645V\n 0101 - 0.688V\n 0110 - 0.731V\n 0111 - 0.774V\n 1000 - 0.817V\n 1001 - 0.860V (default)\n 1010 - 0.903V\n 1011 - 0.946V\n 1100 - 0.989V\n 1101 - 1.032V\n 1110 - 1.075V\n 1111 - 1.118V

`pub fn en(&self) -> EN_R`[src]

Bit 0 - enable\n 0=not enabled, 1=enabled

`impl R<u32, Reg<u32, _CHIP_RESET>>`[src]

`pub fn psm_restart_flag(&self) -> PSM_RESTART_FLAG_R`[src]

Bit 24 - This is set by psm_restart from the debugger.\n Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.

`pub fn had_psm_restart(&self) -> HAD_PSM_RESTART_R`[src]

Bit 20 - Last reset was from the debug port

`pub fn had_run(&self) -> HAD_RUN_R`[src]

Bit 16 - Last reset was from the RUN pin

`pub fn had_por(&self) -> HAD_POR_R`[src]

Bit 8 - Last reset was from the power-on reset or brown-out detection blocks

`impl R<u32, Reg<u32, _PLATFORM>>`[src]

`pub fn fpga(&self) -> FPGA_R`[src]

Bit 1 - Indicates the platform is an FPGA

`pub fn asic(&self) -> ASIC_R`[src]

Bit 0 - Indicates the platform is an ASIC

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH0_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (0).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH1_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (1).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH2_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (2).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH3_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (3).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH4_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (4).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH5_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (5).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH6_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (6).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH7_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (7).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH8_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (8).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH9_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (9).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH10_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (10).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u8, TREQ_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, TREQ_SEL_A>`[src]

Get enumerated values variant

`pub fn is_timer0(&self) -> bool`[src]

Checks if the value of the field is TIMER0

`pub fn is_timer1(&self) -> bool`[src]

Checks if the value of the field is TIMER1

`pub fn is_timer2(&self) -> bool`[src]

Checks if the value of the field is TIMER2

`pub fn is_timer3(&self) -> bool`[src]

Checks if the value of the field is TIMER3

`pub fn is_permanent(&self) -> bool`[src]

Checks if the value of the field is PERMANENT

`impl R<u8, RING_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, RING_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_ring_none(&self) -> bool`[src]

Checks if the value of the field is RING_NONE

`impl R<u8, DATA_SIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATA_SIZE_A>`[src]

Get enumerated values variant

`pub fn is_size_byte(&self) -> bool`[src]

Checks if the value of the field is SIZE_BYTE

`pub fn is_size_halfword(&self) -> bool`[src]

Checks if the value of the field is SIZE_HALFWORD

`pub fn is_size_word(&self) -> bool`[src]

Checks if the value of the field is SIZE_WORD

`impl R<u32, Reg<u32, _CH11_CTRL_TRIG>>`[src]

`pub fn ahb_error(&self) -> AHB_ERROR_R`[src]

Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

`pub fn read_error(&self) -> READ_ERROR_R`[src]

Bit 30 - If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)

`pub fn write_error(&self) -> WRITE_ERROR_R`[src]

Bit 29 - If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)

`pub fn busy(&self) -> BUSY_R`[src]

Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

`pub fn sniff_en(&self) -> SNIFF_EN_R`[src]

Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 22 - Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

`pub fn irq_quiet(&self) -> IRQ_QUIET_R`[src]

Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

`pub fn treq_sel(&self) -> TREQ_SEL_R`[src]

Bits 15:20 - Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ

`pub fn chain_to(&self) -> CHAIN_TO_R`[src]

Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).\n Reset value is equal to channel number (11).

`pub fn ring_sel(&self) -> RING_SEL_R`[src]

Bit 10 - Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

`pub fn ring_size(&self) -> RING_SIZE_R`[src]

Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

`pub fn incr_write(&self) -> INCR_WRITE_R`[src]

Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers.

`pub fn incr_read(&self) -> INCR_READ_R`[src]

Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers.

`pub fn data_size(&self) -> DATA_SIZE_R`[src]

Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

`pub fn high_priority(&self) -> HIGH_PRIORITY_R`[src]

Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

`pub fn en(&self) -> EN_R`[src]

Bit 0 - DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn intr(&self) -> INTR_R`[src]

Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

`impl R<u32, Reg<u32, _INTE0>>`[src]

`pub fn inte0(&self) -> INTE0_R`[src]

Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0.

`impl R<u32, Reg<u32, _INTF0>>`[src]

`pub fn intf0(&self) -> INTF0_R`[src]

Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

`impl R<u32, Reg<u32, _INTS0>>`[src]

`pub fn ints0(&self) -> INTS0_R`[src]

Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here.

`impl R<u32, Reg<u32, _INTE1>>`[src]

`pub fn inte1(&self) -> INTE1_R`[src]

Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1.

`impl R<u32, Reg<u32, _INTF1>>`[src]

`pub fn intf1(&self) -> INTF1_R`[src]

Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

`impl R<u32, Reg<u32, _INTS1>>`[src]

`pub fn ints1(&self) -> INTS1_R`[src]

Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here.

`impl R<u32, Reg<u32, _TIMER0>>`[src]

`pub fn x(&self) -> X_R`[src]

Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

`pub fn y(&self) -> Y_R`[src]

Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

`impl R<u32, Reg<u32, _TIMER1>>`[src]

`pub fn x(&self) -> X_R`[src]

Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

`pub fn y(&self) -> Y_R`[src]

Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

`impl R<u32, Reg<u32, _MULTI_CHAN_TRIGGER>>`[src]

`pub fn multi_chan_trigger(&self) -> MULTI_CHAN_TRIGGER_R`[src]

Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.

`impl R<u8, CALC_A>`[src]

`pub fn variant(&self) -> Variant<u8, CALC_A>`[src]

Get enumerated values variant

`pub fn is_crc32(&self) -> bool`[src]

Checks if the value of the field is CRC32

`pub fn is_crc32r(&self) -> bool`[src]

Checks if the value of the field is CRC32R

`pub fn is_crc16(&self) -> bool`[src]

Checks if the value of the field is CRC16

`pub fn is_crc16r(&self) -> bool`[src]

Checks if the value of the field is CRC16R

`pub fn is_even(&self) -> bool`[src]

Checks if the value of the field is EVEN

`pub fn is_sum(&self) -> bool`[src]

Checks if the value of the field is SUM

`impl R<u32, Reg<u32, _SNIFF_CTRL>>`[src]

`pub fn out_inv(&self) -> OUT_INV_R`[src]

Bit 11 - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

`pub fn out_rev(&self) -> OUT_REV_R`[src]

Bit 10 - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

`pub fn bswap(&self) -> BSWAP_R`[src]

Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.

`pub fn calc(&self) -> CALC_R`[src]

Bits 5:8

`pub fn dmach(&self) -> DMACH_R`[src]

Bits 1:4 - DMA channel for Sniffer to observe

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Enable sniffer

`impl R<u32, Reg<u32, _FIFO_LEVELS>>`[src]

`pub fn raf_lvl(&self) -> RAF_LVL_R`[src]

Bits 16:23 - Current Read-Address-FIFO fill level

`pub fn waf_lvl(&self) -> WAF_LVL_R`[src]

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.

`impl R<u32, Reg<u32, _ADDR_ENDP1>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP2>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP3>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP4>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP5>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP6>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP7>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP8>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP9>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP10>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP11>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP12>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP13>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP14>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _ADDR_ENDP15>>`[src]

`pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R`[src]

Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)

`pub fn intep_dir(&self) -> INTEP_DIR_R`[src]

Bit 25 - Direction of the interrupt endpoint. In=0, Out=1

`pub fn endpoint(&self) -> ENDPOINT_R`[src]

Bits 16:19 - Endpoint number of the interrupt endpoint

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:6 - Device address

`impl R<u32, Reg<u32, _MAIN_CTRL>>`[src]

`pub fn sim_timing(&self) -> SIM_TIMING_R`[src]

Bit 31 - Reduced timings for simulation

`pub fn host_ndevice(&self) -> HOST_NDEVICE_R`[src]

Bit 1 - Device mode = 0, Host mode = 1

`pub fn controller_en(&self) -> CONTROLLER_EN_R`[src]

Bit 0 - Enable controller

`impl R<u32, Reg<u32, _SOF_RD>>`[src]

`pub fn count(&self) -> COUNT_R`[src]

Bits 0:10

`impl R<u32, Reg<u32, _SIE_CTRL>>`[src]

`pub fn ep0_int_stall(&self) -> EP0_INT_STALL_R`[src]

Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL

`pub fn ep0_double_buf(&self) -> EP0_DOUBLE_BUF_R`[src]

Bit 30 - Device: EP0 single buffered = 0, double buffered = 1

`pub fn ep0_int_1buf(&self) -> EP0_INT_1BUF_R`[src]

Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0

`pub fn ep0_int_2buf(&self) -> EP0_INT_2BUF_R`[src]

Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0

`pub fn ep0_int_nak(&self) -> EP0_INT_NAK_R`[src]

Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK

`pub fn direct_en(&self) -> DIRECT_EN_R`[src]

Bit 26 - Direct bus drive enable

`pub fn direct_dp(&self) -> DIRECT_DP_R`[src]

Bit 25 - Direct control of DP

`pub fn direct_dm(&self) -> DIRECT_DM_R`[src]

Bit 24 - Direct control of DM

`pub fn transceiver_pd(&self) -> TRANSCEIVER_PD_R`[src]

Bit 18 - Power down bus transceiver

`pub fn rpu_opt(&self) -> RPU_OPT_R`[src]

Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)

`pub fn pullup_en(&self) -> PULLUP_EN_R`[src]

Bit 16 - Device: Enable pull up resistor

`pub fn pulldown_en(&self) -> PULLDOWN_EN_R`[src]

Bit 15 - Host: Enable pull down resistors

`pub fn reset_bus(&self) -> RESET_BUS_R`[src]

Bit 13 - Host: Reset bus

`pub fn resume(&self) -> RESUME_R`[src]

Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend.

`pub fn vbus_en(&self) -> VBUS_EN_R`[src]

Bit 11 - Host: Enable VBUS

`pub fn keep_alive_en(&self) -> KEEP_ALIVE_EN_R`[src]

Bit 10 - Host: Enable keep alive packet (for low speed bus)

`pub fn sof_en(&self) -> SOF_EN_R`[src]

Bit 9 - Host: Enable SOF generation (for full speed bus)

`pub fn sof_sync(&self) -> SOF_SYNC_R`[src]

Bit 8 - Host: Delay packet(s) until after SOF

`pub fn preamble_en(&self) -> PREAMBLE_EN_R`[src]

Bit 6 - Host: Preable enable for LS device on FS hub

`pub fn stop_trans(&self) -> STOP_TRANS_R`[src]

Bit 4 - Host: Stop transaction

`pub fn receive_data(&self) -> RECEIVE_DATA_R`[src]

Bit 3 - Host: Receive transaction (IN to host)

`pub fn send_data(&self) -> SEND_DATA_R`[src]

Bit 2 - Host: Send transaction (OUT from host)

`pub fn send_setup(&self) -> SEND_SETUP_R`[src]

Bit 1 - Host: Send Setup packet

`pub fn start_trans(&self) -> START_TRANS_R`[src]

Bit 0 - Host: Start transaction

`impl R<u32, Reg<u32, _SIE_STATUS>>`[src]

`pub fn data_seq_error(&self) -> DATA_SEQ_ERROR_R`[src]

Bit 31 - Data Sequence Error.\n\n The device can raise a sequence error in the following conditions:\n\n * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n The host can raise a data sequence error in the following conditions:\n\n * An IN packet from the device has the wrong data PID

`pub fn ack_rec(&self) -> ACK_REC_R`[src]

Bit 30 - ACK received. Raised by both host and device.

`pub fn stall_rec(&self) -> STALL_REC_R`[src]

Bit 29 - Host: STALL received

`pub fn nak_rec(&self) -> NAK_REC_R`[src]

Bit 28 - Host: NAK received

`pub fn rx_timeout(&self) -> RX_TIMEOUT_R`[src]

Bit 27 - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.

`pub fn rx_overflow(&self) -> RX_OVERFLOW_R`[src]

Bit 26 - RX overflow is raised by the Serial RX engine if the incoming data is too fast.

`pub fn bit_stuff_error(&self) -> BIT_STUFF_ERROR_R`[src]

Bit 25 - Bit Stuff Error. Raised by the Serial RX engine.

`pub fn crc_error(&self) -> CRC_ERROR_R`[src]

Bit 24 - CRC Error. Raised by the Serial RX engine.

`pub fn bus_reset(&self) -> BUS_RESET_R`[src]

Bit 19 - Device: bus reset received

`pub fn trans_complete(&self) -> TRANS_COMPLETE_R`[src]

Bit 18 - Transaction complete.\n\n Raised by device if:\n\n * An IN or OUT packet is sent with the LAST_BUFF bit set in the buffer control register\n\n Raised by host if:\n\n * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the LAST_BUFF bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the LAST_BUFF bit is set

`pub fn setup_rec(&self) -> SETUP_REC_R`[src]

Bit 17 - Device: Setup packet received

`pub fn connected(&self) -> CONNECTED_R`[src]

Bit 16 - Device: connected

`pub fn resume(&self) -> RESUME_R`[src]

Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume.

`pub fn vbus_over_curr(&self) -> VBUS_OVER_CURR_R`[src]

Bit 10 - VBUS over current detected

`pub fn speed(&self) -> SPEED_R`[src]

Bits 8:9 - Host: device speed. Disconnected = 00, LS = 01, FS = 10

`pub fn suspended(&self) -> SUSPENDED_R`[src]

Bit 4 - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.

`pub fn line_state(&self) -> LINE_STATE_R`[src]

Bits 2:3 - USB bus line state

`pub fn vbus_detected(&self) -> VBUS_DETECTED_R`[src]

Bit 0 - Device: VBUS Detected

`impl R<u32, Reg<u32, _INT_EP_CTRL>>`[src]

`pub fn int_ep_active(&self) -> INT_EP_ACTIVE_R`[src]

Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15

`impl R<u32, Reg<u32, _BUFF_STATUS>>`[src]

`pub fn ep15_out(&self) -> EP15_OUT_R`[src]

Bit 31

`pub fn ep15_in(&self) -> EP15_IN_R`[src]

Bit 30

`pub fn ep14_out(&self) -> EP14_OUT_R`[src]

Bit 29

`pub fn ep14_in(&self) -> EP14_IN_R`[src]

Bit 28

`pub fn ep13_out(&self) -> EP13_OUT_R`[src]

Bit 27

`pub fn ep13_in(&self) -> EP13_IN_R`[src]

Bit 26

`pub fn ep12_out(&self) -> EP12_OUT_R`[src]

Bit 25

`pub fn ep12_in(&self) -> EP12_IN_R`[src]

Bit 24

`pub fn ep11_out(&self) -> EP11_OUT_R`[src]

Bit 23

`pub fn ep11_in(&self) -> EP11_IN_R`[src]

Bit 22

`pub fn ep10_out(&self) -> EP10_OUT_R`[src]

Bit 21

`pub fn ep10_in(&self) -> EP10_IN_R`[src]

Bit 20

`pub fn ep9_out(&self) -> EP9_OUT_R`[src]

Bit 19

`pub fn ep9_in(&self) -> EP9_IN_R`[src]

Bit 18

`pub fn ep8_out(&self) -> EP8_OUT_R`[src]

Bit 17

`pub fn ep8_in(&self) -> EP8_IN_R`[src]

Bit 16

`pub fn ep7_out(&self) -> EP7_OUT_R`[src]

Bit 15

`pub fn ep7_in(&self) -> EP7_IN_R`[src]

Bit 14

`pub fn ep6_out(&self) -> EP6_OUT_R`[src]

Bit 13

`pub fn ep6_in(&self) -> EP6_IN_R`[src]

Bit 12

`pub fn ep5_out(&self) -> EP5_OUT_R`[src]

Bit 11

`pub fn ep5_in(&self) -> EP5_IN_R`[src]

Bit 10

`pub fn ep4_out(&self) -> EP4_OUT_R`[src]

Bit 9

`pub fn ep4_in(&self) -> EP4_IN_R`[src]

Bit 8

`pub fn ep3_out(&self) -> EP3_OUT_R`[src]

Bit 7

`pub fn ep3_in(&self) -> EP3_IN_R`[src]

Bit 6

`pub fn ep2_out(&self) -> EP2_OUT_R`[src]

Bit 5

`pub fn ep2_in(&self) -> EP2_IN_R`[src]

Bit 4

`pub fn ep1_out(&self) -> EP1_OUT_R`[src]

Bit 3

`pub fn ep1_in(&self) -> EP1_IN_R`[src]

Bit 2

`pub fn ep0_out(&self) -> EP0_OUT_R`[src]

Bit 1

`pub fn ep0_in(&self) -> EP0_IN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _BUFF_CPU_SHOULD_HANDLE>>`[src]

`pub fn ep15_out(&self) -> EP15_OUT_R`[src]

Bit 31

`pub fn ep15_in(&self) -> EP15_IN_R`[src]

Bit 30

`pub fn ep14_out(&self) -> EP14_OUT_R`[src]

Bit 29

`pub fn ep14_in(&self) -> EP14_IN_R`[src]

Bit 28

`pub fn ep13_out(&self) -> EP13_OUT_R`[src]

Bit 27

`pub fn ep13_in(&self) -> EP13_IN_R`[src]

Bit 26

`pub fn ep12_out(&self) -> EP12_OUT_R`[src]

Bit 25

`pub fn ep12_in(&self) -> EP12_IN_R`[src]

Bit 24

`pub fn ep11_out(&self) -> EP11_OUT_R`[src]

Bit 23

`pub fn ep11_in(&self) -> EP11_IN_R`[src]

Bit 22

`pub fn ep10_out(&self) -> EP10_OUT_R`[src]

Bit 21

`pub fn ep10_in(&self) -> EP10_IN_R`[src]

Bit 20

`pub fn ep9_out(&self) -> EP9_OUT_R`[src]

Bit 19

`pub fn ep9_in(&self) -> EP9_IN_R`[src]

Bit 18

`pub fn ep8_out(&self) -> EP8_OUT_R`[src]

Bit 17

`pub fn ep8_in(&self) -> EP8_IN_R`[src]

Bit 16

`pub fn ep7_out(&self) -> EP7_OUT_R`[src]

Bit 15

`pub fn ep7_in(&self) -> EP7_IN_R`[src]

Bit 14

`pub fn ep6_out(&self) -> EP6_OUT_R`[src]

Bit 13

`pub fn ep6_in(&self) -> EP6_IN_R`[src]

Bit 12

`pub fn ep5_out(&self) -> EP5_OUT_R`[src]

Bit 11

`pub fn ep5_in(&self) -> EP5_IN_R`[src]

Bit 10

`pub fn ep4_out(&self) -> EP4_OUT_R`[src]

Bit 9

`pub fn ep4_in(&self) -> EP4_IN_R`[src]

Bit 8

`pub fn ep3_out(&self) -> EP3_OUT_R`[src]

Bit 7

`pub fn ep3_in(&self) -> EP3_IN_R`[src]

Bit 6

`pub fn ep2_out(&self) -> EP2_OUT_R`[src]

Bit 5

`pub fn ep2_in(&self) -> EP2_IN_R`[src]

Bit 4

`pub fn ep1_out(&self) -> EP1_OUT_R`[src]

Bit 3

`pub fn ep1_in(&self) -> EP1_IN_R`[src]

Bit 2

`pub fn ep0_out(&self) -> EP0_OUT_R`[src]

Bit 1

`pub fn ep0_in(&self) -> EP0_IN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _EP_ABORT>>`[src]

`pub fn ep15_out(&self) -> EP15_OUT_R`[src]

Bit 31

`pub fn ep15_in(&self) -> EP15_IN_R`[src]

Bit 30

`pub fn ep14_out(&self) -> EP14_OUT_R`[src]

Bit 29

`pub fn ep14_in(&self) -> EP14_IN_R`[src]

Bit 28

`pub fn ep13_out(&self) -> EP13_OUT_R`[src]

Bit 27

`pub fn ep13_in(&self) -> EP13_IN_R`[src]

Bit 26

`pub fn ep12_out(&self) -> EP12_OUT_R`[src]

Bit 25

`pub fn ep12_in(&self) -> EP12_IN_R`[src]

Bit 24

`pub fn ep11_out(&self) -> EP11_OUT_R`[src]

Bit 23

`pub fn ep11_in(&self) -> EP11_IN_R`[src]

Bit 22

`pub fn ep10_out(&self) -> EP10_OUT_R`[src]

Bit 21

`pub fn ep10_in(&self) -> EP10_IN_R`[src]

Bit 20

`pub fn ep9_out(&self) -> EP9_OUT_R`[src]

Bit 19

`pub fn ep9_in(&self) -> EP9_IN_R`[src]

Bit 18

`pub fn ep8_out(&self) -> EP8_OUT_R`[src]

Bit 17

`pub fn ep8_in(&self) -> EP8_IN_R`[src]

Bit 16

`pub fn ep7_out(&self) -> EP7_OUT_R`[src]

Bit 15

`pub fn ep7_in(&self) -> EP7_IN_R`[src]

Bit 14

`pub fn ep6_out(&self) -> EP6_OUT_R`[src]

Bit 13

`pub fn ep6_in(&self) -> EP6_IN_R`[src]

Bit 12

`pub fn ep5_out(&self) -> EP5_OUT_R`[src]

Bit 11

`pub fn ep5_in(&self) -> EP5_IN_R`[src]

Bit 10

`pub fn ep4_out(&self) -> EP4_OUT_R`[src]

Bit 9

`pub fn ep4_in(&self) -> EP4_IN_R`[src]

Bit 8

`pub fn ep3_out(&self) -> EP3_OUT_R`[src]

Bit 7

`pub fn ep3_in(&self) -> EP3_IN_R`[src]

Bit 6

`pub fn ep2_out(&self) -> EP2_OUT_R`[src]

Bit 5

`pub fn ep2_in(&self) -> EP2_IN_R`[src]

Bit 4

`pub fn ep1_out(&self) -> EP1_OUT_R`[src]

Bit 3

`pub fn ep1_in(&self) -> EP1_IN_R`[src]

Bit 2

`pub fn ep0_out(&self) -> EP0_OUT_R`[src]

Bit 1

`pub fn ep0_in(&self) -> EP0_IN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _EP_ABORT_DONE>>`[src]

`pub fn ep15_out(&self) -> EP15_OUT_R`[src]

Bit 31

`pub fn ep15_in(&self) -> EP15_IN_R`[src]

Bit 30

`pub fn ep14_out(&self) -> EP14_OUT_R`[src]

Bit 29

`pub fn ep14_in(&self) -> EP14_IN_R`[src]

Bit 28

`pub fn ep13_out(&self) -> EP13_OUT_R`[src]

Bit 27

`pub fn ep13_in(&self) -> EP13_IN_R`[src]

Bit 26

`pub fn ep12_out(&self) -> EP12_OUT_R`[src]

Bit 25

`pub fn ep12_in(&self) -> EP12_IN_R`[src]

Bit 24

`pub fn ep11_out(&self) -> EP11_OUT_R`[src]

Bit 23

`pub fn ep11_in(&self) -> EP11_IN_R`[src]

Bit 22

`pub fn ep10_out(&self) -> EP10_OUT_R`[src]

Bit 21

`pub fn ep10_in(&self) -> EP10_IN_R`[src]

Bit 20

`pub fn ep9_out(&self) -> EP9_OUT_R`[src]

Bit 19

`pub fn ep9_in(&self) -> EP9_IN_R`[src]

Bit 18

`pub fn ep8_out(&self) -> EP8_OUT_R`[src]

Bit 17

`pub fn ep8_in(&self) -> EP8_IN_R`[src]

Bit 16

`pub fn ep7_out(&self) -> EP7_OUT_R`[src]

Bit 15

`pub fn ep7_in(&self) -> EP7_IN_R`[src]

Bit 14

`pub fn ep6_out(&self) -> EP6_OUT_R`[src]

Bit 13

`pub fn ep6_in(&self) -> EP6_IN_R`[src]

Bit 12

`pub fn ep5_out(&self) -> EP5_OUT_R`[src]

Bit 11

`pub fn ep5_in(&self) -> EP5_IN_R`[src]

Bit 10

`pub fn ep4_out(&self) -> EP4_OUT_R`[src]

Bit 9

`pub fn ep4_in(&self) -> EP4_IN_R`[src]

Bit 8

`pub fn ep3_out(&self) -> EP3_OUT_R`[src]

Bit 7

`pub fn ep3_in(&self) -> EP3_IN_R`[src]

Bit 6

`pub fn ep2_out(&self) -> EP2_OUT_R`[src]

Bit 5

`pub fn ep2_in(&self) -> EP2_IN_R`[src]

Bit 4

`pub fn ep1_out(&self) -> EP1_OUT_R`[src]

Bit 3

`pub fn ep1_in(&self) -> EP1_IN_R`[src]

Bit 2

`pub fn ep0_out(&self) -> EP0_OUT_R`[src]

Bit 1

`pub fn ep0_in(&self) -> EP0_IN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _EP_STALL_ARM>>`[src]

`pub fn ep0_out(&self) -> EP0_OUT_R`[src]

Bit 1

`pub fn ep0_in(&self) -> EP0_IN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _NAK_POLL>>`[src]

`pub fn delay_fs(&self) -> DELAY_FS_R`[src]

Bits 16:25 - NAK polling interval for a full speed device

`pub fn delay_ls(&self) -> DELAY_LS_R`[src]

Bits 0:9 - NAK polling interval for a low speed device

`impl R<u32, Reg<u32, _EP_STATUS_STALL_NAK>>`[src]

`pub fn ep15_out(&self) -> EP15_OUT_R`[src]

Bit 31

`pub fn ep15_in(&self) -> EP15_IN_R`[src]

Bit 30

`pub fn ep14_out(&self) -> EP14_OUT_R`[src]

Bit 29

`pub fn ep14_in(&self) -> EP14_IN_R`[src]

Bit 28

`pub fn ep13_out(&self) -> EP13_OUT_R`[src]

Bit 27

`pub fn ep13_in(&self) -> EP13_IN_R`[src]

Bit 26

`pub fn ep12_out(&self) -> EP12_OUT_R`[src]

Bit 25

`pub fn ep12_in(&self) -> EP12_IN_R`[src]

Bit 24

`pub fn ep11_out(&self) -> EP11_OUT_R`[src]

Bit 23

`pub fn ep11_in(&self) -> EP11_IN_R`[src]

Bit 22

`pub fn ep10_out(&self) -> EP10_OUT_R`[src]

Bit 21

`pub fn ep10_in(&self) -> EP10_IN_R`[src]

Bit 20

`pub fn ep9_out(&self) -> EP9_OUT_R`[src]

Bit 19

`pub fn ep9_in(&self) -> EP9_IN_R`[src]

Bit 18

`pub fn ep8_out(&self) -> EP8_OUT_R`[src]

Bit 17

`pub fn ep8_in(&self) -> EP8_IN_R`[src]

Bit 16

`pub fn ep7_out(&self) -> EP7_OUT_R`[src]

Bit 15

`pub fn ep7_in(&self) -> EP7_IN_R`[src]

Bit 14

`pub fn ep6_out(&self) -> EP6_OUT_R`[src]

Bit 13

`pub fn ep6_in(&self) -> EP6_IN_R`[src]

Bit 12

`pub fn ep5_out(&self) -> EP5_OUT_R`[src]

Bit 11

`pub fn ep5_in(&self) -> EP5_IN_R`[src]

Bit 10

`pub fn ep4_out(&self) -> EP4_OUT_R`[src]

Bit 9

`pub fn ep4_in(&self) -> EP4_IN_R`[src]

Bit 8

`pub fn ep3_out(&self) -> EP3_OUT_R`[src]

Bit 7

`pub fn ep3_in(&self) -> EP3_IN_R`[src]

Bit 6

`pub fn ep2_out(&self) -> EP2_OUT_R`[src]

Bit 5

`pub fn ep2_in(&self) -> EP2_IN_R`[src]

`pub fn vbus_en_override_en(&self) -> VBUS_EN_OVERRIDE_EN_R`[src]

Bit 1

`pub fn vbus_en(&self) -> VBUS_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _USBPHY_DIRECT>>`[src]

`pub fn dm_ovv(&self) -> DM_OVV_R`[src]

Bit 22 - DM over voltage

`pub fn dp_ovv(&self) -> DP_OVV_R`[src]

Bit 21 - DP over voltage

`pub fn dm_ovcn(&self) -> DM_OVCN_R`[src]

Bit 20 - DM overcurrent

`pub fn dp_ovcn(&self) -> DP_OVCN_R`[src]

Bit 19 - DP overcurrent

`pub fn rx_dm(&self) -> RX_DM_R`[src]

Bit 18 - DPM pin state

`pub fn rx_dp(&self) -> RX_DP_R`[src]

Bit 17 - DPP pin state

`pub fn rx_dd(&self) -> RX_DD_R`[src]

Bit 16 - Differential RX

`pub fn tx_diffmode(&self) -> TX_DIFFMODE_R`[src]

Bit 15 - TX_DIFFMODE=0: Single ended mode\n TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)

`pub fn tx_fsslew(&self) -> TX_FSSLEW_R`[src]

Bit 14 - TX_FSSLEW=0: Low speed slew rate\n TX_FSSLEW=1: Full speed slew rate

`pub fn tx_pd(&self) -> TX_PD_R`[src]

Bit 13 - TX power down override (if override enable is set). 1 = powered down.

`pub fn rx_pd(&self) -> RX_PD_R`[src]

Bit 12 - RX power down override (if override enable is set). 1 = powered down.

`pub fn tx_dm(&self) -> TX_DM_R`[src]

Bit 11 - Output data. TX_DIFFMODE=1, Ignored\n TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM

`pub fn tx_dp(&self) -> TX_DP_R`[src]

Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP

`pub fn tx_dm_oe(&self) -> TX_DM_OE_R`[src]

Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored.\n If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving

`pub fn tx_dp_oe(&self) -> TX_DP_OE_R`[src]

Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving

`pub fn dm_pulldn_en(&self) -> DM_PULLDN_EN_R`[src]

Bit 6 - DM pull down enable

`pub fn dm_pullup_en(&self) -> DM_PULLUP_EN_R`[src]

Bit 5 - DM pull up enable

`pub fn dm_pullup_hisel(&self) -> DM_PULLUP_HISEL_R`[src]

Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2

`pub fn dp_pulldn_en(&self) -> DP_PULLDN_EN_R`[src]

Bit 2 - DP pull down enable

`pub fn dp_pullup_en(&self) -> DP_PULLUP_EN_R`[src]

Bit 1 - DP pull up enable

`pub fn dp_pullup_hisel(&self) -> DP_PULLUP_HISEL_R`[src]

Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2

`impl R<u32, Reg<u32, _USBPHY_DIRECT_OVERRIDE>>`[src]

`pub fn tx_diffmode_override_en(&self) -> TX_DIFFMODE_OVERRIDE_EN_R`[src]

Bit 15

`pub fn dm_pullup_override_en(&self) -> DM_PULLUP_OVERRIDE_EN_R`[src]

Bit 12

`pub fn tx_fsslew_override_en(&self) -> TX_FSSLEW_OVERRIDE_EN_R`[src]

Bit 11

`pub fn tx_pd_override_en(&self) -> TX_PD_OVERRIDE_EN_R`[src]

Bit 10

`pub fn rx_pd_override_en(&self) -> RX_PD_OVERRIDE_EN_R`[src]

Bit 9

`pub fn tx_dm_override_en(&self) -> TX_DM_OVERRIDE_EN_R`[src]

Bit 8

`pub fn tx_dp_override_en(&self) -> TX_DP_OVERRIDE_EN_R`[src]

Bit 7

`pub fn tx_dm_oe_override_en(&self) -> TX_DM_OE_OVERRIDE_EN_R`[src]

Bit 6

`pub fn tx_dp_oe_override_en(&self) -> TX_DP_OE_OVERRIDE_EN_R`[src]

Bit 5

`pub fn dm_pulldn_en_override_en(&self) -> DM_PULLDN_EN_OVERRIDE_EN_R`[src]

Bit 4

`pub fn dp_pulldn_en_override_en(&self) -> DP_PULLDN_EN_OVERRIDE_EN_R`[src]

Bit 3

`pub fn dp_pullup_en_override_en(&self) -> DP_PULLUP_EN_OVERRIDE_EN_R`[src]

Bit 2

`pub fn dm_pullup_hisel_override_en(&self) -> DM_PULLUP_HISEL_OVERRIDE_EN_R`[src]

Bit 1

`pub fn dp_pullup_hisel_override_en(&self) -> DP_PULLUP_HISEL_OVERRIDE_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _USBPHY_TRIM>>`[src]

`pub fn dm_pulldn_trim(&self) -> DM_PULLDN_TRIM_R`[src]

Bits 8:12 - Value to drive to USB PHY\n DM pulldown resistor trim control\n Experimental data suggests that the reset value will work, but this register allows adjustment if required

`pub fn dp_pulldn_trim(&self) -> DP_PULLDN_TRIM_R`[src]

Bits 0:4 - Value to drive to USB PHY\n DP pulldown resistor trim control\n Experimental data suggests that the reset value will work, but this register allows adjustment if required

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R`[src]

Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.

`pub fn abort_done(&self) -> ABORT_DONE_R`[src]

Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.

`pub fn dev_sof(&self) -> DEV_SOF_R`[src]

Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD

`pub fn setup_req(&self) -> SETUP_REQ_R`[src]

Bit 16 - Device. Source: SIE_STATUS.SETUP_REC

`pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R`[src]

Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn dev_suspend(&self) -> DEV_SUSPEND_R`[src]

Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED

`pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R`[src]

Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED

`pub fn bus_reset(&self) -> BUS_RESET_R`[src]

Bit 12 - Source: SIE_STATUS.BUS_RESET

`pub fn vbus_detect(&self) -> VBUS_DETECT_R`[src]

Bit 11 - Source: SIE_STATUS.VBUS_DETECT

`pub fn stall(&self) -> STALL_R`[src]

Bit 10 - Source: SIE_STATUS.STALL_REC

`pub fn error_crc(&self) -> ERROR_CRC_R`[src]

Bit 9 - Source: SIE_STATUS.CRC_ERROR

`pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R`[src]

Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR

`pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R`[src]

Bit 7 - Source: SIE_STATUS.RX_OVERFLOW

`pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R`[src]

Bit 6 - Source: SIE_STATUS.RX_TIMEOUT

`pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R`[src]

Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR

`pub fn buff_status(&self) -> BUFF_STATUS_R`[src]

Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.

`pub fn trans_complete(&self) -> TRANS_COMPLETE_R`[src]

Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.

`pub fn host_sof(&self) -> HOST_SOF_R`[src]

Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD

`pub fn host_resume(&self) -> HOST_RESUME_R`[src]

Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R`[src]

Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED

`impl R<u32, Reg<u32, _INTE>>`[src]

`pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R`[src]

Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.

`pub fn abort_done(&self) -> ABORT_DONE_R`[src]

Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.

`pub fn dev_sof(&self) -> DEV_SOF_R`[src]

Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD

`pub fn setup_req(&self) -> SETUP_REQ_R`[src]

Bit 16 - Device. Source: SIE_STATUS.SETUP_REC

`pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R`[src]

Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn dev_suspend(&self) -> DEV_SUSPEND_R`[src]

Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED

`pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R`[src]

Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED

`pub fn bus_reset(&self) -> BUS_RESET_R`[src]

Bit 12 - Source: SIE_STATUS.BUS_RESET

`pub fn vbus_detect(&self) -> VBUS_DETECT_R`[src]

Bit 11 - Source: SIE_STATUS.VBUS_DETECT

`pub fn stall(&self) -> STALL_R`[src]

Bit 10 - Source: SIE_STATUS.STALL_REC

`pub fn error_crc(&self) -> ERROR_CRC_R`[src]

Bit 9 - Source: SIE_STATUS.CRC_ERROR

`pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R`[src]

Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR

`pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R`[src]

Bit 7 - Source: SIE_STATUS.RX_OVERFLOW

`pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R`[src]

Bit 6 - Source: SIE_STATUS.RX_TIMEOUT

`pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R`[src]

Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR

`pub fn buff_status(&self) -> BUFF_STATUS_R`[src]

Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.

`pub fn trans_complete(&self) -> TRANS_COMPLETE_R`[src]

Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.

`pub fn host_sof(&self) -> HOST_SOF_R`[src]

Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD

`pub fn host_resume(&self) -> HOST_RESUME_R`[src]

Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R`[src]

Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED

`impl R<u32, Reg<u32, _INTF>>`[src]

`pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R`[src]

Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.

`pub fn abort_done(&self) -> ABORT_DONE_R`[src]

Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.

`pub fn dev_sof(&self) -> DEV_SOF_R`[src]

Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD

`pub fn setup_req(&self) -> SETUP_REQ_R`[src]

Bit 16 - Device. Source: SIE_STATUS.SETUP_REC

`pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R`[src]

Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn dev_suspend(&self) -> DEV_SUSPEND_R`[src]

Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED

`pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R`[src]

Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED

`pub fn bus_reset(&self) -> BUS_RESET_R`[src]

Bit 12 - Source: SIE_STATUS.BUS_RESET

`pub fn vbus_detect(&self) -> VBUS_DETECT_R`[src]

Bit 11 - Source: SIE_STATUS.VBUS_DETECT

`pub fn stall(&self) -> STALL_R`[src]

Bit 10 - Source: SIE_STATUS.STALL_REC

`pub fn error_crc(&self) -> ERROR_CRC_R`[src]

Bit 9 - Source: SIE_STATUS.CRC_ERROR

`pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R`[src]

Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR

`pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R`[src]

Bit 7 - Source: SIE_STATUS.RX_OVERFLOW

`pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R`[src]

Bit 6 - Source: SIE_STATUS.RX_TIMEOUT

`pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R`[src]

Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR

`pub fn buff_status(&self) -> BUFF_STATUS_R`[src]

Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.

`pub fn trans_complete(&self) -> TRANS_COMPLETE_R`[src]

Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.

`pub fn host_sof(&self) -> HOST_SOF_R`[src]

Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD

`pub fn host_resume(&self) -> HOST_RESUME_R`[src]

Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R`[src]

Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED

`impl R<u32, Reg<u32, _INTS>>`[src]

`pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R`[src]

Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.

`pub fn abort_done(&self) -> ABORT_DONE_R`[src]

Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.

`pub fn dev_sof(&self) -> DEV_SOF_R`[src]

Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD

`pub fn setup_req(&self) -> SETUP_REQ_R`[src]

Bit 16 - Device. Source: SIE_STATUS.SETUP_REC

`pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R`[src]

Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn dev_suspend(&self) -> DEV_SUSPEND_R`[src]

Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED

`pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R`[src]

Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED

`pub fn bus_reset(&self) -> BUS_RESET_R`[src]

Bit 12 - Source: SIE_STATUS.BUS_RESET

`pub fn vbus_detect(&self) -> VBUS_DETECT_R`[src]

Bit 11 - Source: SIE_STATUS.VBUS_DETECT

`pub fn stall(&self) -> STALL_R`[src]

Bit 10 - Source: SIE_STATUS.STALL_REC

`pub fn error_crc(&self) -> ERROR_CRC_R`[src]

Bit 9 - Source: SIE_STATUS.CRC_ERROR

`pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R`[src]

Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR

`pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R`[src]

Bit 7 - Source: SIE_STATUS.RX_OVERFLOW

`pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R`[src]

Bit 6 - Source: SIE_STATUS.RX_TIMEOUT

`pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R`[src]

Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR

`pub fn buff_status(&self) -> BUFF_STATUS_R`[src]

Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.

`pub fn trans_complete(&self) -> TRANS_COMPLETE_R`[src]

Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.

`pub fn host_sof(&self) -> HOST_SOF_R`[src]

Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD

`pub fn host_resume(&self) -> HOST_RESUME_R`[src]

Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME

`pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R`[src]

Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn clkdiv_restart(&self) -> CLKDIV_RESTART_R`[src]

Bits 8:11 - Force clock dividers to restart their count and clear fractional\n accumulators. Restart multiple dividers to synchronise them.

`pub fn sm_restart(&self) -> SM_RESTART_R`[src]

Bits 4:7 - Clear internal SM state which is otherwise difficult to access\n (e.g. shift counters). Self-clearing.

`pub fn sm_enable(&self) -> SM_ENABLE_R`[src]

Bits 0:3 - Enable state machine

`impl R<u32, Reg<u32, _FSTAT>>`[src]

`pub fn txempty(&self) -> TXEMPTY_R`[src]

Bits 24:27 - State machine TX FIFO is empty

`pub fn txfull(&self) -> TXFULL_R`[src]

Bits 16:19 - State machine TX FIFO is full

`pub fn rxempty(&self) -> RXEMPTY_R`[src]

Bits 8:11 - State machine RX FIFO is empty

`pub fn rxfull(&self) -> RXFULL_R`[src]

Bits 0:3 - State machine RX FIFO is full

`impl R<u32, Reg<u32, _FDEBUG>>`[src]

`pub fn txstall(&self) -> TXSTALL_R`[src]

Bits 24:27 - State machine has stalled on empty TX FIFO. Write 1 to clear.

`pub fn txover(&self) -> TXOVER_R`[src]

Bits 16:19 - TX FIFO overflow has occurred. Write 1 to clear.

`pub fn rxunder(&self) -> RXUNDER_R`[src]

Bits 8:11 - RX FIFO underflow has occurred. Write 1 to clear.

`pub fn rxstall(&self) -> RXSTALL_R`[src]

Bits 0:3 - State machine has stalled on full RX FIFO. Write 1 to clear.

`impl R<u32, Reg<u32, _FLEVEL>>`[src]

`pub fn rx3(&self) -> RX3_R`[src]

Bits 28:31

`pub fn tx3(&self) -> TX3_R`[src]

Bits 24:27

`pub fn rx2(&self) -> RX2_R`[src]

Bits 20:23

`pub fn tx2(&self) -> TX2_R`[src]

Bits 16:19

`pub fn rx1(&self) -> RX1_R`[src]

Bits 12:15

`pub fn tx1(&self) -> TX1_R`[src]

Bits 8:11

`pub fn rx0(&self) -> RX0_R`[src]

Bits 4:7

`pub fn tx0(&self) -> TX0_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _IRQ>>`[src]

`pub fn irq(&self) -> IRQ_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _DBG_CFGINFO>>`[src]

`pub fn imem_size(&self) -> IMEM_SIZE_R`[src]

Bits 16:21 - The size of the instruction memory, measured in units of one instruction

`pub fn sm_count(&self) -> SM_COUNT_R`[src]

`pub fn frac(&self) -> FRAC_R`[src]

Bits 8:15 - Fractional part of clock divider

`impl R<bool, STATUS_SEL_A>`[src]

`pub fn variant(&self) -> STATUS_SEL_A`[src]

Get enumerated values variant

`pub fn is_txlevel(&self) -> bool`[src]

Checks if the value of the field is TXLEVEL

`pub fn is_rxlevel(&self) -> bool`[src]

Checks if the value of the field is RXLEVEL

`impl R<u32, Reg<u32, _SM0_EXECCTRL>>`[src]

`pub fn exec_stalled(&self) -> EXEC_STALLED_R`[src]

Bit 31 - An instruction written to SMx_INSTR is stalled, and latched by the\n state machine. Will clear once the instruction completes.

`pub fn side_en(&self) -> SIDE_EN_R`[src]

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

`pub fn side_pindir(&self) -> SIDE_PINDIR_R`[src]

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

`pub fn jmp_pin(&self) -> JMP_PIN_R`[src]

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

`pub fn out_en_sel(&self) -> OUT_EN_SEL_R`[src]

Bits 19:23 - Which data bit to use for inline OUT enable

`pub fn inline_out_en(&self) -> INLINE_OUT_EN_R`[src]

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

`pub fn out_sticky(&self) -> OUT_STICKY_R`[src]

Bit 17 - Continuously assert the most recent OUT/SET to the pins

`pub fn wrap_top(&self) -> WRAP_TOP_R`[src]

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

`pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R`[src]

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

`pub fn status_sel(&self) -> STATUS_SEL_R`[src]

Bit 4 - Comparison used for the MOV x, STATUS instruction.

`pub fn status_n(&self) -> STATUS_N_R`[src]

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

`impl R<u32, Reg<u32, _SM0_SHIFTCTRL>>`[src]

`pub fn fjoin_rx(&self) -> FJOIN_RX_R`[src]

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn fjoin_tx(&self) -> FJOIN_TX_R`[src]

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn pull_thresh(&self) -> PULL_THRESH_R`[src]

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

`pub fn push_thresh(&self) -> PUSH_THRESH_R`[src]

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

`pub fn out_shiftdir(&self) -> OUT_SHIFTDIR_R`[src]

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

`pub fn in_shiftdir(&self) -> IN_SHIFTDIR_R`[src]

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

`pub fn autopull(&self) -> AUTOPULL_R`[src]

Bit 17 - Pull automatically when the output shift register is emptied

`pub fn autopush(&self) -> AUTOPUSH_R`[src]

Bit 16 - Push automatically when the input shift register is filled

`impl R<u32, Reg<u32, _SM0_ADDR>>`[src]

`pub fn sm0_addr(&self) -> SM0_ADDR_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _SM0_INSTR>>`[src]

`pub fn sm0_instr(&self) -> SM0_INSTR_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SM0_PINCTRL>>`[src]

`pub fn sideset_count(&self) -> SIDESET_COUNT_R`[src]

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

`pub fn set_count(&self) -> SET_COUNT_R`[src]

Bits 26:28 - The number of pins asserted by a SET. Max of 5

`pub fn out_count(&self) -> OUT_COUNT_R`[src]

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

`pub fn in_base(&self) -> IN_BASE_R`[src]

Bits 15:19 - The virtual pin corresponding to IN bit 0

`pub fn sideset_base(&self) -> SIDESET_BASE_R`[src]

Bits 10:14 - The virtual pin corresponding to delay field bit 0

`pub fn set_base(&self) -> SET_BASE_R`[src]

Bits 5:9 - The virtual pin corresponding to SET bit 0

`pub fn out_base(&self) -> OUT_BASE_R`[src]

Bits 0:4 - The virtual pin corresponding to OUT bit 0

`impl R<u32, Reg<u32, _SM1_CLKDIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

`pub fn frac(&self) -> FRAC_R`[src]

Bits 8:15 - Fractional part of clock divider

`impl R<bool, STATUS_SEL_A>`[src]

`pub fn variant(&self) -> STATUS_SEL_A`[src]

Get enumerated values variant

`pub fn is_txlevel(&self) -> bool`[src]

Checks if the value of the field is TXLEVEL

`pub fn is_rxlevel(&self) -> bool`[src]

Checks if the value of the field is RXLEVEL

`impl R<u32, Reg<u32, _SM1_EXECCTRL>>`[src]

`pub fn exec_stalled(&self) -> EXEC_STALLED_R`[src]

Bit 31 - An instruction written to SMx_INSTR is stalled, and latched by the\n state machine. Will clear once the instruction completes.

`pub fn side_en(&self) -> SIDE_EN_R`[src]

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

`pub fn side_pindir(&self) -> SIDE_PINDIR_R`[src]

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

`pub fn jmp_pin(&self) -> JMP_PIN_R`[src]

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

`pub fn out_en_sel(&self) -> OUT_EN_SEL_R`[src]

Bits 19:23 - Which data bit to use for inline OUT enable

`pub fn inline_out_en(&self) -> INLINE_OUT_EN_R`[src]

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

`pub fn out_sticky(&self) -> OUT_STICKY_R`[src]

Bit 17 - Continuously assert the most recent OUT/SET to the pins

`pub fn wrap_top(&self) -> WRAP_TOP_R`[src]

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

`pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R`[src]

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

`pub fn status_sel(&self) -> STATUS_SEL_R`[src]

Bit 4 - Comparison used for the MOV x, STATUS instruction.

`pub fn status_n(&self) -> STATUS_N_R`[src]

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

`impl R<u32, Reg<u32, _SM1_SHIFTCTRL>>`[src]

`pub fn fjoin_rx(&self) -> FJOIN_RX_R`[src]

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn fjoin_tx(&self) -> FJOIN_TX_R`[src]

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn pull_thresh(&self) -> PULL_THRESH_R`[src]

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

`pub fn push_thresh(&self) -> PUSH_THRESH_R`[src]

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

`pub fn out_shiftdir(&self) -> OUT_SHIFTDIR_R`[src]

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

`pub fn in_shiftdir(&self) -> IN_SHIFTDIR_R`[src]

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

`pub fn autopull(&self) -> AUTOPULL_R`[src]

Bit 17 - Pull automatically when the output shift register is emptied

`pub fn autopush(&self) -> AUTOPUSH_R`[src]

Bit 16 - Push automatically when the input shift register is filled

`impl R<u32, Reg<u32, _SM1_ADDR>>`[src]

`pub fn sm1_addr(&self) -> SM1_ADDR_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _SM1_INSTR>>`[src]

`pub fn sm1_instr(&self) -> SM1_INSTR_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SM1_PINCTRL>>`[src]

`pub fn sideset_count(&self) -> SIDESET_COUNT_R`[src]

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

`pub fn set_count(&self) -> SET_COUNT_R`[src]

Bits 26:28 - The number of pins asserted by a SET. Max of 5

`pub fn out_count(&self) -> OUT_COUNT_R`[src]

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

`pub fn in_base(&self) -> IN_BASE_R`[src]

Bits 15:19 - The virtual pin corresponding to IN bit 0

`pub fn sideset_base(&self) -> SIDESET_BASE_R`[src]

Bits 10:14 - The virtual pin corresponding to delay field bit 0

`pub fn set_base(&self) -> SET_BASE_R`[src]

Bits 5:9 - The virtual pin corresponding to SET bit 0

`pub fn out_base(&self) -> OUT_BASE_R`[src]

Bits 0:4 - The virtual pin corresponding to OUT bit 0

`impl R<u32, Reg<u32, _SM2_CLKDIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

`pub fn frac(&self) -> FRAC_R`[src]

Bits 8:15 - Fractional part of clock divider

`impl R<bool, STATUS_SEL_A>`[src]

`pub fn variant(&self) -> STATUS_SEL_A`[src]

Get enumerated values variant

`pub fn is_txlevel(&self) -> bool`[src]

Checks if the value of the field is TXLEVEL

`pub fn is_rxlevel(&self) -> bool`[src]

Checks if the value of the field is RXLEVEL

`impl R<u32, Reg<u32, _SM2_EXECCTRL>>`[src]

`pub fn exec_stalled(&self) -> EXEC_STALLED_R`[src]

Bit 31 - An instruction written to SMx_INSTR is stalled, and latched by the\n state machine. Will clear once the instruction completes.

`pub fn side_en(&self) -> SIDE_EN_R`[src]

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

`pub fn side_pindir(&self) -> SIDE_PINDIR_R`[src]

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

`pub fn jmp_pin(&self) -> JMP_PIN_R`[src]

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

`pub fn out_en_sel(&self) -> OUT_EN_SEL_R`[src]

Bits 19:23 - Which data bit to use for inline OUT enable

`pub fn inline_out_en(&self) -> INLINE_OUT_EN_R`[src]

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

`pub fn out_sticky(&self) -> OUT_STICKY_R`[src]

Bit 17 - Continuously assert the most recent OUT/SET to the pins

`pub fn wrap_top(&self) -> WRAP_TOP_R`[src]

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

`pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R`[src]

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

`pub fn status_sel(&self) -> STATUS_SEL_R`[src]

Bit 4 - Comparison used for the MOV x, STATUS instruction.

`pub fn status_n(&self) -> STATUS_N_R`[src]

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

`impl R<u32, Reg<u32, _SM2_SHIFTCTRL>>`[src]

`pub fn fjoin_rx(&self) -> FJOIN_RX_R`[src]

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn fjoin_tx(&self) -> FJOIN_TX_R`[src]

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn pull_thresh(&self) -> PULL_THRESH_R`[src]

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

`pub fn push_thresh(&self) -> PUSH_THRESH_R`[src]

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

`pub fn out_shiftdir(&self) -> OUT_SHIFTDIR_R`[src]

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

`pub fn in_shiftdir(&self) -> IN_SHIFTDIR_R`[src]

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

`pub fn autopull(&self) -> AUTOPULL_R`[src]

Bit 17 - Pull automatically when the output shift register is emptied

`pub fn autopush(&self) -> AUTOPUSH_R`[src]

Bit 16 - Push automatically when the input shift register is filled

`impl R<u32, Reg<u32, _SM2_ADDR>>`[src]

`pub fn sm2_addr(&self) -> SM2_ADDR_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _SM2_INSTR>>`[src]

`pub fn sm2_instr(&self) -> SM2_INSTR_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SM2_PINCTRL>>`[src]

`pub fn sideset_count(&self) -> SIDESET_COUNT_R`[src]

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

`pub fn set_count(&self) -> SET_COUNT_R`[src]

Bits 26:28 - The number of pins asserted by a SET. Max of 5

`pub fn out_count(&self) -> OUT_COUNT_R`[src]

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

`pub fn in_base(&self) -> IN_BASE_R`[src]

Bits 15:19 - The virtual pin corresponding to IN bit 0

`pub fn sideset_base(&self) -> SIDESET_BASE_R`[src]

Bits 10:14 - The virtual pin corresponding to delay field bit 0

`pub fn set_base(&self) -> SET_BASE_R`[src]

Bits 5:9 - The virtual pin corresponding to SET bit 0

`pub fn out_base(&self) -> OUT_BASE_R`[src]

Bits 0:4 - The virtual pin corresponding to OUT bit 0

`impl R<u32, Reg<u32, _SM3_CLKDIV>>`[src]

`pub fn int(&self) -> INT_R`[src]

Bits 16:31 - Effective frequency is sysclk/int.\n Value of 0 is interpreted as max possible value

`pub fn frac(&self) -> FRAC_R`[src]

Bits 8:15 - Fractional part of clock divider

`impl R<bool, STATUS_SEL_A>`[src]

`pub fn variant(&self) -> STATUS_SEL_A`[src]

Get enumerated values variant

`pub fn is_txlevel(&self) -> bool`[src]

Checks if the value of the field is TXLEVEL

`pub fn is_rxlevel(&self) -> bool`[src]

Checks if the value of the field is RXLEVEL

`impl R<u32, Reg<u32, _SM3_EXECCTRL>>`[src]

`pub fn exec_stalled(&self) -> EXEC_STALLED_R`[src]

Bit 31 - An instruction written to SMx_INSTR is stalled, and latched by the\n state machine. Will clear once the instruction completes.

`pub fn side_en(&self) -> SIDE_EN_R`[src]

Bit 30 - If 1, the delay MSB is used as side-set enable, rather than a\n side-set data bit. This allows instructions to perform side-set optionally,\n rather than on every instruction.

`pub fn side_pindir(&self) -> SIDE_PINDIR_R`[src]

Bit 29 - Side-set data is asserted to pin OEs instead of pin values

`pub fn jmp_pin(&self) -> JMP_PIN_R`[src]

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

`pub fn out_en_sel(&self) -> OUT_EN_SEL_R`[src]

Bits 19:23 - Which data bit to use for inline OUT enable

`pub fn inline_out_en(&self) -> INLINE_OUT_EN_R`[src]

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)

`pub fn out_sticky(&self) -> OUT_STICKY_R`[src]

Bit 17 - Continuously assert the most recent OUT/SET to the pins

`pub fn wrap_top(&self) -> WRAP_TOP_R`[src]

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority.

`pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R`[src]

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

`pub fn status_sel(&self) -> STATUS_SEL_R`[src]

Bit 4 - Comparison used for the MOV x, STATUS instruction.

`pub fn status_n(&self) -> STATUS_N_R`[src]

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

`impl R<u32, Reg<u32, _SM3_SHIFTCTRL>>`[src]

`pub fn fjoin_rx(&self) -> FJOIN_RX_R`[src]

Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn fjoin_tx(&self) -> FJOIN_TX_R`[src]

Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed.

`pub fn pull_thresh(&self) -> PULL_THRESH_R`[src]

Bits 25:29 - Number of bits shifted out of TXSR before autopull or conditional pull.\n Write 0 for value of 32.

`pub fn push_thresh(&self) -> PUSH_THRESH_R`[src]

Bits 20:24 - Number of bits shifted into RXSR before autopush or conditional push.\n Write 0 for value of 32.

`pub fn out_shiftdir(&self) -> OUT_SHIFTDIR_R`[src]

Bit 19 - 1 = shift out of output shift register to right. 0 = to left.

`pub fn in_shiftdir(&self) -> IN_SHIFTDIR_R`[src]

Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left.

`pub fn autopull(&self) -> AUTOPULL_R`[src]

Bit 17 - Pull automatically when the output shift register is emptied

`pub fn autopush(&self) -> AUTOPUSH_R`[src]

Bit 16 - Push automatically when the input shift register is filled

`impl R<u32, Reg<u32, _SM3_ADDR>>`[src]

`pub fn sm3_addr(&self) -> SM3_ADDR_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _SM3_INSTR>>`[src]

`pub fn sm3_instr(&self) -> SM3_INSTR_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SM3_PINCTRL>>`[src]

`pub fn sideset_count(&self) -> SIDESET_COUNT_R`[src]

Bits 29:31 - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present.

`pub fn set_count(&self) -> SET_COUNT_R`[src]

Bits 26:28 - The number of pins asserted by a SET. Max of 5

`pub fn out_count(&self) -> OUT_COUNT_R`[src]

Bits 20:25 - The number of pins asserted by an OUT. Value of 0 -> 32 pins

`pub fn in_base(&self) -> IN_BASE_R`[src]

Bits 15:19 - The virtual pin corresponding to IN bit 0

`pub fn sideset_base(&self) -> SIDESET_BASE_R`[src]

Bits 10:14 - The virtual pin corresponding to delay field bit 0

`pub fn set_base(&self) -> SET_BASE_R`[src]

Bits 5:9 - The virtual pin corresponding to SET bit 0

`pub fn out_base(&self) -> OUT_BASE_R`[src]

Bits 0:4 - The virtual pin corresponding to OUT bit 0

`impl R<u32, Reg<u32, _INTR>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _IRQ0_INTE>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _IRQ0_INTF>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _IRQ0_INTS>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _IRQ1_INTE>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _IRQ1_INTF>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _IRQ1_INTS>>`[src]

`pub fn sm3(&self) -> SM3_R`[src]

Bit 11

`pub fn sm2(&self) -> SM2_R`[src]

Bit 10

`pub fn sm1(&self) -> SM1_R`[src]

Bit 9

`pub fn sm0(&self) -> SM0_R`[src]

Bit 8

`pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R`[src]

Bit 7

`pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R`[src]

Bit 6

`pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R`[src]

Bit 5

`pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R`[src]

Bit 4

`pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R`[src]

Bit 3

`pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R`[src]

Bit 2

`pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R`[src]

Bit 1

`pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _GPIO_IN>>`[src]

`pub fn gpio_in(&self) -> GPIO_IN_R`[src]

Bits 0:29 - Input value for GPIO0...29

`impl R<u32, Reg<u32, _GPIO_HI_IN>>`[src]

`pub fn gpio_hi_in(&self) -> GPIO_HI_IN_R`[src]

Bits 0:5 - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3

`impl R<u32, Reg<u32, _GPIO_OUT>>`[src]

`pub fn gpio_out(&self) -> GPIO_OUT_R`[src]

Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29.\n Reading back gives the last value written, NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

`impl R<u32, Reg<u32, _GPIO_OUT_SET>>`[src]

`pub fn gpio_out_set(&self) -> GPIO_OUT_SET_R`[src]

Bits 0:29 - Perform an atomic bit-set on GPIO_OUT, i.e. GPIO_OUT |= wdata

`impl R<u32, Reg<u32, _GPIO_OUT_CLR>>`[src]

`pub fn gpio_out_clr(&self) -> GPIO_OUT_CLR_R`[src]

Bits 0:29 - Perform an atomic bit-clear on GPIO_OUT, i.e. GPIO_OUT &= ~wdata

`impl R<u32, Reg<u32, _GPIO_OUT_XOR>>`[src]

`pub fn gpio_out_xor(&self) -> GPIO_OUT_XOR_R`[src]

Bits 0:29 - Perform an atomic bitwise XOR on GPIO_OUT, i.e. GPIO_OUT ^= wdata

`impl R<u32, Reg<u32, _GPIO_OE>>`[src]

`pub fn gpio_oe(&self) -> GPIO_OE_R`[src]

Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

`impl R<u32, Reg<u32, _GPIO_OE_SET>>`[src]

`pub fn gpio_oe_set(&self) -> GPIO_OE_SET_R`[src]

Bits 0:29 - Perform an atomic bit-set on GPIO_OE, i.e. GPIO_OE |= wdata

`impl R<u32, Reg<u32, _GPIO_OE_CLR>>`[src]

`pub fn gpio_oe_clr(&self) -> GPIO_OE_CLR_R`[src]

Bits 0:29 - Perform an atomic bit-clear on GPIO_OE, i.e. GPIO_OE &= ~wdata

`impl R<u32, Reg<u32, _GPIO_OE_XOR>>`[src]

`pub fn gpio_oe_xor(&self) -> GPIO_OE_XOR_R`[src]

Bits 0:29 - Perform an atomic bitwise XOR on GPIO_OE, i.e. GPIO_OE ^= wdata

`impl R<u32, Reg<u32, _GPIO_HI_OUT>>`[src]

`pub fn gpio_hi_out(&self) -> GPIO_HI_OUT_R`[src]

Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5.\n Reading back gives the last value written, NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

`impl R<u32, Reg<u32, _GPIO_HI_OUT_SET>>`[src]

`pub fn gpio_hi_out_set(&self) -> GPIO_HI_OUT_SET_R`[src]

Bits 0:5 - Perform an atomic bit-set on GPIO_HI_OUT, i.e. GPIO_HI_OUT |= wdata

`impl R<u32, Reg<u32, _GPIO_HI_OUT_CLR>>`[src]

`pub fn gpio_hi_out_clr(&self) -> GPIO_HI_OUT_CLR_R`[src]

Bits 0:5 - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. GPIO_HI_OUT &= ~wdata

`impl R<u32, Reg<u32, _GPIO_HI_OUT_XOR>>`[src]

`pub fn gpio_hi_out_xor(&self) -> GPIO_HI_OUT_XOR_R`[src]

Bits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. GPIO_HI_OUT ^= wdata

`impl R<u32, Reg<u32, _GPIO_HI_OE>>`[src]

`pub fn gpio_hi_oe(&self) -> GPIO_HI_OE_R`[src]

Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result.

`impl R<u32, Reg<u32, _GPIO_HI_OE_SET>>`[src]

`pub fn gpio_hi_oe_set(&self) -> GPIO_HI_OE_SET_R`[src]

Bits 0:5 - Perform an atomic bit-set on GPIO_HI_OE, i.e. GPIO_HI_OE |= wdata

`impl R<u32, Reg<u32, _GPIO_HI_OE_CLR>>`[src]

`pub fn gpio_hi_oe_clr(&self) -> GPIO_HI_OE_CLR_R`[src]

Bits 0:5 - Perform an atomic bit-clear on GPIO_HI_OE, i.e. GPIO_HI_OE &= ~wdata

`impl R<u32, Reg<u32, _GPIO_HI_OE_XOR>>`[src]

`pub fn gpio_hi_oe_xor(&self) -> GPIO_HI_OE_XOR_R`[src]

Bits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. GPIO_HI_OE ^= wdata

`impl R<u32, Reg<u32, _FIFO_ST>>`[src]

`pub fn roe(&self) -> ROE_R`[src]

Bit 3 - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.

`pub fn wof(&self) -> WOF_R`[src]

Bit 2 - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.

`pub fn rdy(&self) -> RDY_R`[src]

Bit 1 - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)

`pub fn vld(&self) -> VLD_R`[src]

Bit 0 - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)

`impl R<u32, Reg<u32, _DIV_CSR>>`[src]

`pub fn dirty(&self) -> DIRTY_R`[src]

Bit 1 - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n If the flag is used in this way, it's recommended to either read QUOTIENT only,\n or REMAINDER and then QUOTIENT, to prevent data loss on context switch.

`pub fn ready(&self) -> READY_R`[src]

Bit 0 - Reads as 0 when a calculation is in progress, 1 otherwise.\n Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n matter if one is already in progress.\n Writing to a result register will immediately terminate any in-progress calculation\n and set the READY and DIRTY flags.

`impl R<u32, Reg<u32, _INTERP0_CTRL_LANE0>>`[src]

`pub fn overf(&self) -> OVERF_R`[src]

Bit 25 - Set if either OVERF0 or OVERF1 is set.

`pub fn overf1(&self) -> OVERF1_R`[src]

Bit 24 - Indicates if any masked-off MSBs in ACCUM1 are set.

`pub fn overf0(&self) -> OVERF0_R`[src]

Bit 23 - Indicates if any masked-off MSBs in ACCUM0 are set.

`pub fn blend(&self) -> BLEND_R`[src]

Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled:\n - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n 0 and 255/256ths)\n - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

`pub fn force_msb(&self) -> FORCE_MSB_R`[src]

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

`pub fn add_raw(&self) -> ADD_RAW_R`[src]

Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

`pub fn cross_result(&self) -> CROSS_RESULT_R`[src]

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

`pub fn cross_input(&self) -> CROSS_INPUT_R`[src]

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

`pub fn signed(&self) -> SIGNED_R`[src]

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

`pub fn mask_msb(&self) -> MASK_MSB_R`[src]

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

`pub fn mask_lsb(&self) -> MASK_LSB_R`[src]

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

`pub fn shift(&self) -> SHIFT_R`[src]

Bits 0:4 - Logical right-shift applied to accumulator before masking

`impl R<u32, Reg<u32, _INTERP0_CTRL_LANE1>>`[src]

`pub fn force_msb(&self) -> FORCE_MSB_R`[src]

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

`pub fn add_raw(&self) -> ADD_RAW_R`[src]

Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

`pub fn cross_result(&self) -> CROSS_RESULT_R`[src]

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

`pub fn cross_input(&self) -> CROSS_INPUT_R`[src]

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

`pub fn signed(&self) -> SIGNED_R`[src]

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

`pub fn mask_msb(&self) -> MASK_MSB_R`[src]

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

`pub fn mask_lsb(&self) -> MASK_LSB_R`[src]

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

`pub fn shift(&self) -> SHIFT_R`[src]

Bits 0:4 - Logical right-shift applied to accumulator before masking

`impl R<u32, Reg<u32, _INTERP0_ACCUM0_ADD>>`[src]

`pub fn interp0_accum0_add(&self) -> INTERP0_ACCUM0_ADD_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _INTERP0_ACCUM1_ADD>>`[src]

`pub fn interp0_accum1_add(&self) -> INTERP0_ACCUM1_ADD_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _INTERP1_CTRL_LANE0>>`[src]

`pub fn overf(&self) -> OVERF_R`[src]

Bit 25 - Set if either OVERF0 or OVERF1 is set.

`pub fn overf1(&self) -> OVERF1_R`[src]

Bit 24 - Indicates if any masked-off MSBs in ACCUM1 are set.

`pub fn overf0(&self) -> OVERF0_R`[src]

Bit 23 - Indicates if any masked-off MSBs in ACCUM0 are set.

`pub fn clamp(&self) -> CLAMP_R`[src]

Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled:\n - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n BASE0 and an upper bound of BASE1.\n - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

`pub fn force_msb(&self) -> FORCE_MSB_R`[src]

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

`pub fn add_raw(&self) -> ADD_RAW_R`[src]

Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

`pub fn cross_result(&self) -> CROSS_RESULT_R`[src]

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

`pub fn cross_input(&self) -> CROSS_INPUT_R`[src]

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

`pub fn signed(&self) -> SIGNED_R`[src]

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

`pub fn mask_msb(&self) -> MASK_MSB_R`[src]

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

`pub fn mask_lsb(&self) -> MASK_LSB_R`[src]

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

`pub fn shift(&self) -> SHIFT_R`[src]

Bits 0:4 - Logical right-shift applied to accumulator before masking

`impl R<u32, Reg<u32, _INTERP1_CTRL_LANE1>>`[src]

`pub fn force_msb(&self) -> FORCE_MSB_R`[src]

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM.

`pub fn add_raw(&self) -> ADD_RAW_R`[src]

Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

`pub fn cross_result(&self) -> CROSS_RESULT_R`[src]

Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.

`pub fn cross_input(&self) -> CROSS_INPUT_R`[src]

Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

`pub fn signed(&self) -> SIGNED_R`[src]

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

`pub fn mask_msb(&self) -> MASK_MSB_R`[src]

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out

`pub fn mask_lsb(&self) -> MASK_LSB_R`[src]

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

`pub fn shift(&self) -> SHIFT_R`[src]

Bits 0:4 - Logical right-shift applied to accumulator before masking

`impl R<u32, Reg<u32, _INTERP1_ACCUM0_ADD>>`[src]

`pub fn interp1_accum0_add(&self) -> INTERP1_ACCUM0_ADD_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _INTERP1_ACCUM1_ADD>>`[src]

`pub fn interp1_accum1_add(&self) -> INTERP1_ACCUM1_ADD_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _SYST_CSR>>`[src]

`pub fn countflag(&self) -> COUNTFLAG_R`[src]

Bit 16 - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.

`pub fn clksource(&self) -> CLKSOURCE_R`[src]

Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n Selects the SysTick timer clock source:\n 0 = External reference clock.\n 1 = Processor clock.

`pub fn tickint(&self) -> TICKINT_R`[src]

Bit 1 - Enables SysTick exception request:\n 0 = Counting down to zero does not assert the SysTick exception request.\n 1 = Counting down to zero to asserts the SysTick exception request.

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - Enable SysTick counter:\n 0 = Counter disabled.\n 1 = Counter enabled.

`impl R<u32, Reg<u32, _SYST_RVR>>`[src]

`pub fn reload(&self) -> RELOAD_R`[src]

Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0.

`impl R<u32, Reg<u32, _SYST_CVR>>`[src]

`pub fn current(&self) -> CURRENT_R`[src]

Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.

`impl R<u32, Reg<u32, _SYST_CALIB>>`[src]

`pub fn noref(&self) -> NOREF_R`[src]

Bit 31 - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.

`pub fn skew(&self) -> SKEW_R`[src]

Bit 30 - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).

`pub fn tenms(&self) -> TENMS_R`[src]

Bits 0:23 - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.

`impl R<u32, Reg<u32, _NVIC_ISER>>`[src]

`pub fn setena(&self) -> SETENA_R`[src]

Bits 0:31 - Interrupt set-enable bits.\n Write:\n 0 = No effect.\n 1 = Enable interrupt.\n Read:\n 0 = Interrupt disabled.\n 1 = Interrupt enabled.

`impl R<u32, Reg<u32, _NVIC_ICER>>`[src]

`pub fn clrena(&self) -> CLRENA_R`[src]

Bits 0:31 - Interrupt clear-enable bits.\n Write:\n 0 = No effect.\n 1 = Disable interrupt.\n Read:\n 0 = Interrupt disabled.\n 1 = Interrupt enabled.

`impl R<u32, Reg<u32, _NVIC_ISPR>>`[src]

`pub fn setpend(&self) -> SETPEND_R`[src]

Bits 0:31 - Interrupt set-pending bits.\n Write:\n 0 = No effect.\n 1 = Changes interrupt state to pending.\n Read:\n 0 = Interrupt is not pending.\n 1 = Interrupt is pending.\n Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n An interrupt that is pending has no effect.\n A disabled interrupt sets the state of that interrupt to pending.

`impl R<u32, Reg<u32, _NVIC_ICPR>>`[src]

`pub fn clrpend(&self) -> CLRPEND_R`[src]

Bits 0:31 - Interrupt clear-pending bits.\n Write:\n 0 = No effect.\n 1 = Removes pending state and interrupt.\n Read:\n 0 = Interrupt is not pending.\n 1 = Interrupt is pending.

`impl R<u32, Reg<u32, _NVIC_IPR0>>`[src]

`pub fn ip_3(&self) -> IP_3_R`[src]

Bits 30:31 - Priority of interrupt 3

`pub fn ip_2(&self) -> IP_2_R`[src]

Bits 22:23 - Priority of interrupt 2

`pub fn ip_1(&self) -> IP_1_R`[src]

Bits 14:15 - Priority of interrupt 1

`pub fn ip_0(&self) -> IP_0_R`[src]

Bits 6:7 - Priority of interrupt 0

`impl R<u32, Reg<u32, _NVIC_IPR1>>`[src]

`pub fn ip_7(&self) -> IP_7_R`[src]

Bits 30:31 - Priority of interrupt 7

`pub fn ip_6(&self) -> IP_6_R`[src]

Bits 22:23 - Priority of interrupt 6

`pub fn ip_5(&self) -> IP_5_R`[src]

Bits 14:15 - Priority of interrupt 5

`pub fn ip_4(&self) -> IP_4_R`[src]

Bits 6:7 - Priority of interrupt 4

`impl R<u32, Reg<u32, _NVIC_IPR2>>`[src]

`pub fn ip_11(&self) -> IP_11_R`[src]

Bits 30:31 - Priority of interrupt 11

`pub fn ip_10(&self) -> IP_10_R`[src]

Bits 22:23 - Priority of interrupt 10

`pub fn ip_9(&self) -> IP_9_R`[src]

Bits 14:15 - Priority of interrupt 9

`pub fn ip_8(&self) -> IP_8_R`[src]

Bits 6:7 - Priority of interrupt 8

`impl R<u32, Reg<u32, _NVIC_IPR3>>`[src]

`pub fn ip_15(&self) -> IP_15_R`[src]

Bits 30:31 - Priority of interrupt 15

`pub fn ip_14(&self) -> IP_14_R`[src]

Bits 22:23 - Priority of interrupt 14

`pub fn ip_13(&self) -> IP_13_R`[src]

Bits 14:15 - Priority of interrupt 13

`pub fn ip_12(&self) -> IP_12_R`[src]

Bits 6:7 - Priority of interrupt 12

`impl R<u32, Reg<u32, _NVIC_IPR4>>`[src]

`pub fn ip_19(&self) -> IP_19_R`[src]

Bits 30:31 - Priority of interrupt 19

`pub fn ip_18(&self) -> IP_18_R`[src]

Bits 22:23 - Priority of interrupt 18

`pub fn ip_17(&self) -> IP_17_R`[src]

Bits 14:15 - Priority of interrupt 17

`pub fn ip_16(&self) -> IP_16_R`[src]

Bits 6:7 - Priority of interrupt 16

`impl R<u32, Reg<u32, _NVIC_IPR5>>`[src]

`pub fn ip_23(&self) -> IP_23_R`[src]

Bits 30:31 - Priority of interrupt 23

`pub fn ip_22(&self) -> IP_22_R`[src]

Bits 22:23 - Priority of interrupt 22

`pub fn ip_21(&self) -> IP_21_R`[src]

Bits 14:15 - Priority of interrupt 21

`pub fn ip_20(&self) -> IP_20_R`[src]

Bits 6:7 - Priority of interrupt 20

`impl R<u32, Reg<u32, _NVIC_IPR6>>`[src]

`pub fn ip_27(&self) -> IP_27_R`[src]

Bits 30:31 - Priority of interrupt 27

`pub fn ip_26(&self) -> IP_26_R`[src]

Bits 22:23 - Priority of interrupt 26

`pub fn ip_25(&self) -> IP_25_R`[src]

Bits 14:15 - Priority of interrupt 25

`pub fn ip_24(&self) -> IP_24_R`[src]

Bits 6:7 - Priority of interrupt 24

`impl R<u32, Reg<u32, _NVIC_IPR7>>`[src]

`pub fn ip_31(&self) -> IP_31_R`[src]

Bits 30:31 - Priority of interrupt 31

`pub fn ip_30(&self) -> IP_30_R`[src]

Bits 22:23 - Priority of interrupt 30

`pub fn ip_29(&self) -> IP_29_R`[src]

Bits 14:15 - Priority of interrupt 29

`pub fn ip_28(&self) -> IP_28_R`[src]

Bits 6:7 - Priority of interrupt 28

`impl R<u32, Reg<u32, _CPUID>>`[src]

`pub fn implementer(&self) -> IMPLEMENTER_R`[src]

Bits 24:31 - Implementor code: 0x41 = ARM

`pub fn variant(&self) -> VARIANT_R`[src]

Bits 20:23 - Major revision number n in the rnpm revision status:\n 0x0 = Revision 0.

`pub fn architecture(&self) -> ARCHITECTURE_R`[src]

Bits 16:19 - Constant that defines the architecture of the processor:\n 0xC = ARMv6-M architecture.

`pub fn partno(&self) -> PARTNO_R`[src]

Bits 4:15 - Number of processor within family: 0xC60 = Cortex-M0+

`pub fn revision(&self) -> REVISION_R`[src]

Bits 0:3 - Minor revision number m in the rnpm revision status:\n 0x1 = Patch 1.

`impl R<u32, Reg<u32, _ICSR>>`[src]

`pub fn nmipendset(&self) -> NMIPENDSET_R`[src]

Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n NMI set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes NMI exception state to pending.\n Read:\n 0 = NMI exception is not pending.\n 1 = NMI exception is pending.\n Because NMI is the highest-priority exception, normally the processor enters the NMI\n exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n NMI signal is reasserted while the processor is executing that handler.

`pub fn pendsvset(&self) -> PENDSVSET_R`[src]

Bit 28 - PendSV set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes PendSV exception state to pending.\n Read:\n 0 = PendSV exception is not pending.\n 1 = PendSV exception is pending.\n Writing 1 to this bit is the only way to set the PendSV exception state to pending.

`pub fn pendsvclr(&self) -> PENDSVCLR_R`[src]

Bit 27 - PendSV clear-pending bit.\n Write:\n 0 = No effect.\n 1 = Removes the pending state from the PendSV exception.

`pub fn pendstset(&self) -> PENDSTSET_R`[src]

Bit 26 - SysTick exception set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes SysTick exception state to pending.\n Read:\n 0 = SysTick exception is not pending.\n 1 = SysTick exception is pending.

`pub fn pendstclr(&self) -> PENDSTCLR_R`[src]

Bit 25 - SysTick exception clear-pending bit.\n Write:\n 0 = No effect.\n 1 = Removes the pending state from the SysTick exception.\n This bit is WO. On a register read its value is Unknown.

`pub fn isrpreempt(&self) -> ISRPREEMPT_R`[src]

Bit 23 - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.

`pub fn isrpending(&self) -> ISRPENDING_R`[src]

Bit 22 - External interrupt pending flag

`pub fn vectpending(&self) -> VECTPENDING_R`[src]

Bits 12:20 - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.

`pub fn vectactive(&self) -> VECTACTIVE_R`[src]

Bits 0:8 - Active exception number field. Reset clears the VECTACTIVE field.

`impl R<u32, Reg<u32, _VTOR>>`[src]

`pub fn tbloff(&self) -> TBLOFF_R`[src]

Bits 8:31 - Bits [31:8] of the indicate the vector table offset address.

`impl R<u32, Reg<u32, _AIRCR>>`[src]

`pub fn vectkey(&self) -> VECTKEY_R`[src]

Bits 16:31 - Register key:\n Reads as Unknown\n On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.

`pub fn endianess(&self) -> ENDIANESS_R`[src]

Bit 15 - Data endianness implemented:\n 0 = Little-endian.

`pub fn sysresetreq(&self) -> SYSRESETREQ_R`[src]

Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.

`pub fn vectclractive(&self) -> VECTCLRACTIVE_R`[src]

Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.

`impl R<u32, Reg<u32, _SCR>>`[src]

`pub fn sevonpend(&self) -> SEVONPEND_R`[src]

Bit 4 - Send Event on Pending bit:\n 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n processor is not waiting for an event, the event is registered and affects the next WFE.\n The processor also wakes up on execution of an SEV instruction or an external event.

`pub fn sleepdeep(&self) -> SLEEPDEEP_R`[src]

Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode:\n 0 = Sleep.\n 1 = Deep sleep.

`pub fn sleeponexit(&self) -> SLEEPONEXIT_R`[src]

Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n 0 = Do not sleep when returning to Thread mode.\n 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn stkalign(&self) -> STKALIGN_R`[src]

Bit 9 - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.

`pub fn unalign_trp(&self) -> UNALIGN_TRP_R`[src]

Bit 3 - Always reads as one, indicates that all unaligned accesses generate a HardFault.

`impl R<u32, Reg<u32, _SHPR2>>`[src]

`pub fn pri_11(&self) -> PRI_11_R`[src]

Bits 30:31 - Priority of system handler 11, SVCall

`impl R<u32, Reg<u32, _SHPR3>>`[src]

`pub fn pri_15(&self) -> PRI_15_R`[src]

Bits 30:31 - Priority of system handler 15, SysTick

`pub fn pri_14(&self) -> PRI_14_R`[src]

Bits 22:23 - Priority of system handler 14, PendSV

`impl R<u32, Reg<u32, _SHCSR>>`[src]

`pub fn svcallpended(&self) -> SVCALLPENDED_R`[src]

Bit 15 - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.

`impl R<u32, Reg<u32, _MPU_TYPE>>`[src]

`pub fn iregion(&self) -> IREGION_R`[src]

Bits 16:23 - Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.

`pub fn dregion(&self) -> DREGION_R`[src]

Bits 8:15 - Number of regions supported by the MPU.

`pub fn separate(&self) -> SEPARATE_R`[src]

Bit 0 - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.

`impl R<u32, Reg<u32, _MPU_CTRL>>`[src]

`pub fn privdefena(&self) -> PRIVDEFENA_R`[src]

Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n covered by any enabled region causes a fault.\n 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.

`pub fn hfnmiena(&self) -> HFNMIENA_R`[src]

Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n When the MPU is enabled:\n 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n 1 = the MPU is enabled during HardFault and NMI handlers.

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n 0 = MPU disabled.\n 1 = MPU enabled.

`impl R<u32, Reg<u32, _MPU_RNR>>`[src]

`pub fn region(&self) -> REGION_R`[src]

Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n The MPU supports 8 memory regions, so the permitted values of this field are 0-7.

`impl R<u32, Reg<u32, _MPU_RBAR>>`[src]

`pub fn addr(&self) -> ADDR_R`[src]

Bits 8:31 - Base address of the region.

`pub fn valid(&self) -> VALID_R`[src]

Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n Write:\n 0 = MPU_RNR not changed, and the processor:\n Updates the base address for the region specified in the MPU_RNR.\n Ignores the value of the REGION field.\n 1 = The processor:\n Updates the value of the MPU_RNR to the value of the REGION field.\n Updates the base address for the region specified in the REGION field.\n Always reads as zero.

`pub fn region(&self) -> REGION_R`[src]

Bits 0:3 - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.

`impl R<u32, Reg<u32, _MPU_RASR>>`[src]

`pub fn attrs(&self) -> ATTRS_R`[src]

Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control.\n 28 = XN: Instruction access disable bit:\n 0 = Instruction fetches enabled.\n 1 = Instruction fetches disabled.\n 26:24 = AP: Access permission field\n 18 = S: Shareable bit\n 17 = C: Cacheable bit\n 16 = B: Bufferable bit

`pub fn srd(&self) -> SRD_R`[src]

Bits 8:15 - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.

`pub fn size(&self) -> SIZE_R`[src]

Bits 1:5 - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - Enables the region.

Trait Implementations

`impl<U, T, FI> PartialEq<FI> for R<U, T> where U: PartialEq, FI: Copy + Into,` [src]

`pub fn eq(&self, other: &FI) -> bool`[src]

`#[must_use]pub fn ne(&self, other: &Rhs) -> bool`1.0.0[src]

Auto Trait Implementations

`impl<U, T> Send for R<U, T> where T: Send, U: Send,` [src]

`impl<U, T> Sync for R<U, T> where T: Sync, U: Sync,` [src]

`impl<U, T> Unpin for R<U, T> where T: Unpin, U: Unpin,` [src]

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`pub fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`pub fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`pub fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`pub fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`pub fn into(self) -> U`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`pub fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct rp2040::generic::R

Implementations

impl<U, T> R<U, T> where U: Copy, [src]

pub fn bits(&self) -> U[src]

impl<FI> R<bool, FI>[src]

pub fn bit(&self) -> bool[src]

pub fn bit_is_clear(&self) -> bool[src]

pub fn bit_is_set(&self) -> bool[src]

impl R<u32, Reg<u32, _CTRL>>[src]

pub fn power_down(&self) -> POWER_DOWN_R[src]

pub fn err_badwrite(&self) -> ERR_BADWRITE_R[src]

pub fn en(&self) -> EN_R[src]

impl R<u32, Reg<u32, _FLUSH>>[src]

pub fn flush(&self) -> FLUSH_R[src]

impl R<u32, Reg<u32, _STAT>>[src]

pub fn fifo_full(&self) -> FIFO_FULL_R[src]

pub fn fifo_empty(&self) -> FIFO_EMPTY_R[src]

pub fn flush_ready(&self) -> FLUSH_READY_R[src]

impl R<u32, Reg<u32, _STREAM_ADDR>>[src]

pub fn stream_addr(&self) -> STREAM_ADDR_R[src]

impl R<u32, Reg<u32, _STREAM_CTR>>[src]

pub fn stream_ctr(&self) -> STREAM_CTR_R[src]

impl R<u8, SPI_FRF_A>[src]

pub fn variant(&self) -> Variant<u8, SPI_FRF_A>[src]

pub fn is_std(&self) -> bool[src]

pub fn is_dual(&self) -> bool[src]

pub fn is_quad(&self) -> bool[src]

impl R<u8, TMOD_A>[src]

pub fn variant(&self) -> TMOD_A[src]

pub fn is_tx_and_rx(&self) -> bool[src]

pub fn is_tx_only(&self) -> bool[src]

pub fn is_rx_only(&self) -> bool[src]

pub fn is_eeprom_read(&self) -> bool[src]

impl R<u32, Reg<u32, _CTRLR0>>[src]

pub fn sste(&self) -> SSTE_R[src]

pub fn spi_frf(&self) -> SPI_FRF_R[src]

pub fn dfs_32(&self) -> DFS_32_R[src]

pub fn cfs(&self) -> CFS_R[src]

pub fn srl(&self) -> SRL_R[src]

pub fn slv_oe(&self) -> SLV_OE_R[src]

pub fn tmod(&self) -> TMOD_R[src]

pub fn scpol(&self) -> SCPOL_R[src]

pub fn scph(&self) -> SCPH_R[src]

pub fn frf(&self) -> FRF_R[src]

pub fn dfs(&self) -> DFS_R[src]

impl R<u32, Reg<u32, _CTRLR1>>[src]

pub fn ndf(&self) -> NDF_R[src]

impl R<u32, Reg<u32, _SSIENR>>[src]

pub fn ssi_en(&self) -> SSI_EN_R[src]

impl R<u32, Reg<u32, _MWCR>>[src]

pub fn mhs(&self) -> MHS_R[src]

pub fn mdd(&self) -> MDD_R[src]

pub fn mwmod(&self) -> MWMOD_R[src]

impl R<u32, Reg<u32, _SER>>[src]

pub fn ser(&self) -> SER_R[src]

impl R<u32, Reg<u32, _BAUDR>>[src]

pub fn sckdv(&self) -> SCKDV_R[src]

impl R<u32, Reg<u32, _TXFTLR>>[src]

pub fn tft(&self) -> TFT_R[src]

impl R<u32, Reg<u32, _RXFTLR>>[src]

pub fn rft(&self) -> RFT_R[src]

impl R<u32, Reg<u32, _TXFLR>>[src]

pub fn tftfl(&self) -> TFTFL_R[src]

impl R<u32, Reg<u32, _RXFLR>>[src]

pub fn rxtfl(&self) -> RXTFL_R[src]

impl R<u32, Reg<u32, _SR>>[src]

pub fn dcol(&self) -> DCOL_R[src]

pub fn txe(&self) -> TXE_R[src]

pub fn rff(&self) -> RFF_R[src]

pub fn rfne(&self) -> RFNE_R[src]

pub fn tfe(&self) -> TFE_R[src]

pub fn tfnf(&self) -> TFNF_R[src]

pub fn busy(&self) -> BUSY_R[src]

impl R<u32, Reg<u32, _IMR>>[src]

pub fn mstim(&self) -> MSTIM_R[src]

pub fn rxfim(&self) -> RXFIM_R[src]

pub fn rxoim(&self) -> RXOIM_R[src]

pub fn rxuim(&self) -> RXUIM_R[src]

pub fn txoim(&self) -> TXOIM_R[src]

pub fn txeim(&self) -> TXEIM_R[src]

`impl<U, T> R<U, T> where U: Copy,` [src]

`pub fn bits(&self) -> U`[src]

`impl<FI> R<bool, FI>`[src]

`pub fn bit(&self) -> bool`[src]

`pub fn bit_is_clear(&self) -> bool`[src]

`pub fn bit_is_set(&self) -> bool`[src]

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn power_down(&self) -> POWER_DOWN_R`[src]

`pub fn err_badwrite(&self) -> ERR_BADWRITE_R`[src]

`pub fn en(&self) -> EN_R`[src]

`impl R<u32, Reg<u32, _FLUSH>>`[src]

`pub fn flush(&self) -> FLUSH_R`[src]

`impl R<u32, Reg<u32, _STAT>>`[src]

`pub fn fifo_full(&self) -> FIFO_FULL_R`[src]

`pub fn fifo_empty(&self) -> FIFO_EMPTY_R`[src]

`pub fn flush_ready(&self) -> FLUSH_READY_R`[src]

`impl R<u32, Reg<u32, _STREAM_ADDR>>`[src]

`pub fn stream_addr(&self) -> STREAM_ADDR_R`[src]

`impl R<u32, Reg<u32, _STREAM_CTR>>`[src]

`pub fn stream_ctr(&self) -> STREAM_CTR_R`[src]

`impl R<u8, SPI_FRF_A>`[src]

`pub fn variant(&self) -> Variant<u8, SPI_FRF_A>`[src]

`pub fn is_std(&self) -> bool`[src]

`pub fn is_dual(&self) -> bool`[src]

`pub fn is_quad(&self) -> bool`[src]

`impl R<u8, TMOD_A>`[src]

`pub fn variant(&self) -> TMOD_A`[src]

`pub fn is_tx_and_rx(&self) -> bool`[src]

`pub fn is_tx_only(&self) -> bool`[src]

`pub fn is_rx_only(&self) -> bool`[src]

`pub fn is_eeprom_read(&self) -> bool`[src]

`impl R<u32, Reg<u32, _CTRLR0>>`[src]

`pub fn sste(&self) -> SSTE_R`[src]

`pub fn spi_frf(&self) -> SPI_FRF_R`[src]

`pub fn dfs_32(&self) -> DFS_32_R`[src]

`pub fn cfs(&self) -> CFS_R`[src]

`pub fn srl(&self) -> SRL_R`[src]

`pub fn slv_oe(&self) -> SLV_OE_R`[src]

`pub fn tmod(&self) -> TMOD_R`[src]

`pub fn scpol(&self) -> SCPOL_R`[src]

`pub fn scph(&self) -> SCPH_R`[src]

`pub fn frf(&self) -> FRF_R`[src]

`pub fn dfs(&self) -> DFS_R`[src]

`impl R<u32, Reg<u32, _CTRLR1>>`[src]

`pub fn ndf(&self) -> NDF_R`[src]

`impl R<u32, Reg<u32, _SSIENR>>`[src]

`pub fn ssi_en(&self) -> SSI_EN_R`[src]

`impl R<u32, Reg<u32, _MWCR>>`[src]

`pub fn mhs(&self) -> MHS_R`[src]

`pub fn mdd(&self) -> MDD_R`[src]

`pub fn mwmod(&self) -> MWMOD_R`[src]

`impl R<u32, Reg<u32, _SER>>`[src]

`pub fn ser(&self) -> SER_R`[src]

`impl R<u32, Reg<u32, _BAUDR>>`[src]

`pub fn sckdv(&self) -> SCKDV_R`[src]

`impl R<u32, Reg<u32, _TXFTLR>>`[src]

`pub fn tft(&self) -> TFT_R`[src]

`impl R<u32, Reg<u32, _RXFTLR>>`[src]

`pub fn rft(&self) -> RFT_R`[src]

`impl R<u32, Reg<u32, _TXFLR>>`[src]

`pub fn tftfl(&self) -> TFTFL_R`[src]

`impl R<u32, Reg<u32, _RXFLR>>`[src]

`pub fn rxtfl(&self) -> RXTFL_R`[src]

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn dcol(&self) -> DCOL_R`[src]

`pub fn txe(&self) -> TXE_R`[src]

`pub fn rff(&self) -> RFF_R`[src]

`pub fn rfne(&self) -> RFNE_R`[src]

`pub fn tfe(&self) -> TFE_R`[src]

`pub fn tfnf(&self) -> TFNF_R`[src]

`pub fn busy(&self) -> BUSY_R`[src]

`impl R<u32, Reg<u32, _IMR>>`[src]

`pub fn mstim(&self) -> MSTIM_R`[src]

`pub fn rxfim(&self) -> RXFIM_R`[src]

`pub fn rxoim(&self) -> RXOIM_R`[src]

`pub fn rxuim(&self) -> RXUIM_R`[src]

`pub fn txoim(&self) -> TXOIM_R`[src]

`pub fn txeim(&self) -> TXEIM_R`[src]

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn mstis(&self) -> MSTIS_R`[src]