[−][src]Struct rp2040::dma::RegisterBlock
Register block
Fields
ch0_read_addr: CH0_READ_ADDR0x00 - DMA Channel 0 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch0_write_addr: CH0_WRITE_ADDR0x04 - DMA Channel 0 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch0_trans_count: CH0_TRANS_COUNT0x08 - DMA Channel 0 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch0_ctrl_trig: CH0_CTRL_TRIG0x0c - DMA Channel 0 Control and Status
ch0_al1_ctrl: CH0_AL1_CTRL0x10 - Alias for channel 0 CTRL register
ch0_al1_read_addr: CH0_AL1_READ_ADDR0x14 - Alias for channel 0 READ_ADDR register
ch0_al1_write_addr: CH0_AL1_WRITE_ADDR0x18 - Alias for channel 0 WRITE_ADDR register
ch0_al1_trans_count_trig: CH0_AL1_TRANS_COUNT_TRIG0x1c - Alias for channel 0 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch0_al2_ctrl: CH0_AL2_CTRL0x20 - Alias for channel 0 CTRL register
ch0_al2_trans_count: CH0_AL2_TRANS_COUNT0x24 - Alias for channel 0 TRANS_COUNT register
ch0_al2_read_addr: CH0_AL2_READ_ADDR0x28 - Alias for channel 0 READ_ADDR register
ch0_al2_write_addr_trig: CH0_AL2_WRITE_ADDR_TRIG0x2c - Alias for channel 0 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch0_al3_ctrl: CH0_AL3_CTRL0x30 - Alias for channel 0 CTRL register
ch0_al3_write_addr: CH0_AL3_WRITE_ADDR0x34 - Alias for channel 0 WRITE_ADDR register
ch0_al3_trans_count: CH0_AL3_TRANS_COUNT0x38 - Alias for channel 0 TRANS_COUNT register
ch0_al3_read_addr_trig: CH0_AL3_READ_ADDR_TRIG0x3c - Alias for channel 0 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch1_read_addr: CH1_READ_ADDR0x40 - DMA Channel 1 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch1_write_addr: CH1_WRITE_ADDR0x44 - DMA Channel 1 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch1_trans_count: CH1_TRANS_COUNT0x48 - DMA Channel 1 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch1_ctrl_trig: CH1_CTRL_TRIG0x4c - DMA Channel 1 Control and Status
ch1_al1_ctrl: CH1_AL1_CTRL0x50 - Alias for channel 1 CTRL register
ch1_al1_read_addr: CH1_AL1_READ_ADDR0x54 - Alias for channel 1 READ_ADDR register
ch1_al1_write_addr: CH1_AL1_WRITE_ADDR0x58 - Alias for channel 1 WRITE_ADDR register
ch1_al1_trans_count_trig: CH1_AL1_TRANS_COUNT_TRIG0x5c - Alias for channel 1 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch1_al2_ctrl: CH1_AL2_CTRL0x60 - Alias for channel 1 CTRL register
ch1_al2_trans_count: CH1_AL2_TRANS_COUNT0x64 - Alias for channel 1 TRANS_COUNT register
ch1_al2_read_addr: CH1_AL2_READ_ADDR0x68 - Alias for channel 1 READ_ADDR register
ch1_al2_write_addr_trig: CH1_AL2_WRITE_ADDR_TRIG0x6c - Alias for channel 1 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch1_al3_ctrl: CH1_AL3_CTRL0x70 - Alias for channel 1 CTRL register
ch1_al3_write_addr: CH1_AL3_WRITE_ADDR0x74 - Alias for channel 1 WRITE_ADDR register
ch1_al3_trans_count: CH1_AL3_TRANS_COUNT0x78 - Alias for channel 1 TRANS_COUNT register
ch1_al3_read_addr_trig: CH1_AL3_READ_ADDR_TRIG0x7c - Alias for channel 1 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch2_read_addr: CH2_READ_ADDR0x80 - DMA Channel 2 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch2_write_addr: CH2_WRITE_ADDR0x84 - DMA Channel 2 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch2_trans_count: CH2_TRANS_COUNT0x88 - DMA Channel 2 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch2_ctrl_trig: CH2_CTRL_TRIG0x8c - DMA Channel 2 Control and Status
ch2_al1_ctrl: CH2_AL1_CTRL0x90 - Alias for channel 2 CTRL register
ch2_al1_read_addr: CH2_AL1_READ_ADDR0x94 - Alias for channel 2 READ_ADDR register
ch2_al1_write_addr: CH2_AL1_WRITE_ADDR0x98 - Alias for channel 2 WRITE_ADDR register
ch2_al1_trans_count_trig: CH2_AL1_TRANS_COUNT_TRIG0x9c - Alias for channel 2 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch2_al2_ctrl: CH2_AL2_CTRL0xa0 - Alias for channel 2 CTRL register
ch2_al2_trans_count: CH2_AL2_TRANS_COUNT0xa4 - Alias for channel 2 TRANS_COUNT register
ch2_al2_read_addr: CH2_AL2_READ_ADDR0xa8 - Alias for channel 2 READ_ADDR register
ch2_al2_write_addr_trig: CH2_AL2_WRITE_ADDR_TRIG0xac - Alias for channel 2 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch2_al3_ctrl: CH2_AL3_CTRL0xb0 - Alias for channel 2 CTRL register
ch2_al3_write_addr: CH2_AL3_WRITE_ADDR0xb4 - Alias for channel 2 WRITE_ADDR register
ch2_al3_trans_count: CH2_AL3_TRANS_COUNT0xb8 - Alias for channel 2 TRANS_COUNT register
ch2_al3_read_addr_trig: CH2_AL3_READ_ADDR_TRIG0xbc - Alias for channel 2 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch3_read_addr: CH3_READ_ADDR0xc0 - DMA Channel 3 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch3_write_addr: CH3_WRITE_ADDR0xc4 - DMA Channel 3 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch3_trans_count: CH3_TRANS_COUNT0xc8 - DMA Channel 3 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch3_ctrl_trig: CH3_CTRL_TRIG0xcc - DMA Channel 3 Control and Status
ch3_al1_ctrl: CH3_AL1_CTRL0xd0 - Alias for channel 3 CTRL register
ch3_al1_read_addr: CH3_AL1_READ_ADDR0xd4 - Alias for channel 3 READ_ADDR register
ch3_al1_write_addr: CH3_AL1_WRITE_ADDR0xd8 - Alias for channel 3 WRITE_ADDR register
ch3_al1_trans_count_trig: CH3_AL1_TRANS_COUNT_TRIG0xdc - Alias for channel 3 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch3_al2_ctrl: CH3_AL2_CTRL0xe0 - Alias for channel 3 CTRL register
ch3_al2_trans_count: CH3_AL2_TRANS_COUNT0xe4 - Alias for channel 3 TRANS_COUNT register
ch3_al2_read_addr: CH3_AL2_READ_ADDR0xe8 - Alias for channel 3 READ_ADDR register
ch3_al2_write_addr_trig: CH3_AL2_WRITE_ADDR_TRIG0xec - Alias for channel 3 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch3_al3_ctrl: CH3_AL3_CTRL0xf0 - Alias for channel 3 CTRL register
ch3_al3_write_addr: CH3_AL3_WRITE_ADDR0xf4 - Alias for channel 3 WRITE_ADDR register
ch3_al3_trans_count: CH3_AL3_TRANS_COUNT0xf8 - Alias for channel 3 TRANS_COUNT register
ch3_al3_read_addr_trig: CH3_AL3_READ_ADDR_TRIG0xfc - Alias for channel 3 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch4_read_addr: CH4_READ_ADDR0x100 - DMA Channel 4 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch4_write_addr: CH4_WRITE_ADDR0x104 - DMA Channel 4 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch4_trans_count: CH4_TRANS_COUNT0x108 - DMA Channel 4 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch4_ctrl_trig: CH4_CTRL_TRIG0x10c - DMA Channel 4 Control and Status
ch4_al1_ctrl: CH4_AL1_CTRL0x110 - Alias for channel 4 CTRL register
ch4_al1_read_addr: CH4_AL1_READ_ADDR0x114 - Alias for channel 4 READ_ADDR register
ch4_al1_write_addr: CH4_AL1_WRITE_ADDR0x118 - Alias for channel 4 WRITE_ADDR register
ch4_al1_trans_count_trig: CH4_AL1_TRANS_COUNT_TRIG0x11c - Alias for channel 4 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch4_al2_ctrl: CH4_AL2_CTRL0x120 - Alias for channel 4 CTRL register
ch4_al2_trans_count: CH4_AL2_TRANS_COUNT0x124 - Alias for channel 4 TRANS_COUNT register
ch4_al2_read_addr: CH4_AL2_READ_ADDR0x128 - Alias for channel 4 READ_ADDR register
ch4_al2_write_addr_trig: CH4_AL2_WRITE_ADDR_TRIG0x12c - Alias for channel 4 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch4_al3_ctrl: CH4_AL3_CTRL0x130 - Alias for channel 4 CTRL register
ch4_al3_write_addr: CH4_AL3_WRITE_ADDR0x134 - Alias for channel 4 WRITE_ADDR register
ch4_al3_trans_count: CH4_AL3_TRANS_COUNT0x138 - Alias for channel 4 TRANS_COUNT register
ch4_al3_read_addr_trig: CH4_AL3_READ_ADDR_TRIG0x13c - Alias for channel 4 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch5_read_addr: CH5_READ_ADDR0x140 - DMA Channel 5 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch5_write_addr: CH5_WRITE_ADDR0x144 - DMA Channel 5 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch5_trans_count: CH5_TRANS_COUNT0x148 - DMA Channel 5 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch5_ctrl_trig: CH5_CTRL_TRIG0x14c - DMA Channel 5 Control and Status
ch5_al1_ctrl: CH5_AL1_CTRL0x150 - Alias for channel 5 CTRL register
ch5_al1_read_addr: CH5_AL1_READ_ADDR0x154 - Alias for channel 5 READ_ADDR register
ch5_al1_write_addr: CH5_AL1_WRITE_ADDR0x158 - Alias for channel 5 WRITE_ADDR register
ch5_al1_trans_count_trig: CH5_AL1_TRANS_COUNT_TRIG0x15c - Alias for channel 5 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch5_al2_ctrl: CH5_AL2_CTRL0x160 - Alias for channel 5 CTRL register
ch5_al2_trans_count: CH5_AL2_TRANS_COUNT0x164 - Alias for channel 5 TRANS_COUNT register
ch5_al2_read_addr: CH5_AL2_READ_ADDR0x168 - Alias for channel 5 READ_ADDR register
ch5_al2_write_addr_trig: CH5_AL2_WRITE_ADDR_TRIG0x16c - Alias for channel 5 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch5_al3_ctrl: CH5_AL3_CTRL0x170 - Alias for channel 5 CTRL register
ch5_al3_write_addr: CH5_AL3_WRITE_ADDR0x174 - Alias for channel 5 WRITE_ADDR register
ch5_al3_trans_count: CH5_AL3_TRANS_COUNT0x178 - Alias for channel 5 TRANS_COUNT register
ch5_al3_read_addr_trig: CH5_AL3_READ_ADDR_TRIG0x17c - Alias for channel 5 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch6_read_addr: CH6_READ_ADDR0x180 - DMA Channel 6 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch6_write_addr: CH6_WRITE_ADDR0x184 - DMA Channel 6 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch6_trans_count: CH6_TRANS_COUNT0x188 - DMA Channel 6 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch6_ctrl_trig: CH6_CTRL_TRIG0x18c - DMA Channel 6 Control and Status
ch6_al1_ctrl: CH6_AL1_CTRL0x190 - Alias for channel 6 CTRL register
ch6_al1_read_addr: CH6_AL1_READ_ADDR0x194 - Alias for channel 6 READ_ADDR register
ch6_al1_write_addr: CH6_AL1_WRITE_ADDR0x198 - Alias for channel 6 WRITE_ADDR register
ch6_al1_trans_count_trig: CH6_AL1_TRANS_COUNT_TRIG0x19c - Alias for channel 6 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch6_al2_ctrl: CH6_AL2_CTRL0x1a0 - Alias for channel 6 CTRL register
ch6_al2_trans_count: CH6_AL2_TRANS_COUNT0x1a4 - Alias for channel 6 TRANS_COUNT register
ch6_al2_read_addr: CH6_AL2_READ_ADDR0x1a8 - Alias for channel 6 READ_ADDR register
ch6_al2_write_addr_trig: CH6_AL2_WRITE_ADDR_TRIG0x1ac - Alias for channel 6 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch6_al3_ctrl: CH6_AL3_CTRL0x1b0 - Alias for channel 6 CTRL register
ch6_al3_write_addr: CH6_AL3_WRITE_ADDR0x1b4 - Alias for channel 6 WRITE_ADDR register
ch6_al3_trans_count: CH6_AL3_TRANS_COUNT0x1b8 - Alias for channel 6 TRANS_COUNT register
ch6_al3_read_addr_trig: CH6_AL3_READ_ADDR_TRIG0x1bc - Alias for channel 6 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch7_read_addr: CH7_READ_ADDR0x1c0 - DMA Channel 7 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch7_write_addr: CH7_WRITE_ADDR0x1c4 - DMA Channel 7 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch7_trans_count: CH7_TRANS_COUNT0x1c8 - DMA Channel 7 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch7_ctrl_trig: CH7_CTRL_TRIG0x1cc - DMA Channel 7 Control and Status
ch7_al1_ctrl: CH7_AL1_CTRL0x1d0 - Alias for channel 7 CTRL register
ch7_al1_read_addr: CH7_AL1_READ_ADDR0x1d4 - Alias for channel 7 READ_ADDR register
ch7_al1_write_addr: CH7_AL1_WRITE_ADDR0x1d8 - Alias for channel 7 WRITE_ADDR register
ch7_al1_trans_count_trig: CH7_AL1_TRANS_COUNT_TRIG0x1dc - Alias for channel 7 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch7_al2_ctrl: CH7_AL2_CTRL0x1e0 - Alias for channel 7 CTRL register
ch7_al2_trans_count: CH7_AL2_TRANS_COUNT0x1e4 - Alias for channel 7 TRANS_COUNT register
ch7_al2_read_addr: CH7_AL2_READ_ADDR0x1e8 - Alias for channel 7 READ_ADDR register
ch7_al2_write_addr_trig: CH7_AL2_WRITE_ADDR_TRIG0x1ec - Alias for channel 7 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch7_al3_ctrl: CH7_AL3_CTRL0x1f0 - Alias for channel 7 CTRL register
ch7_al3_write_addr: CH7_AL3_WRITE_ADDR0x1f4 - Alias for channel 7 WRITE_ADDR register
ch7_al3_trans_count: CH7_AL3_TRANS_COUNT0x1f8 - Alias for channel 7 TRANS_COUNT register
ch7_al3_read_addr_trig: CH7_AL3_READ_ADDR_TRIG0x1fc - Alias for channel 7 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch8_read_addr: CH8_READ_ADDR0x200 - DMA Channel 8 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch8_write_addr: CH8_WRITE_ADDR0x204 - DMA Channel 8 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch8_trans_count: CH8_TRANS_COUNT0x208 - DMA Channel 8 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch8_ctrl_trig: CH8_CTRL_TRIG0x20c - DMA Channel 8 Control and Status
ch8_al1_ctrl: CH8_AL1_CTRL0x210 - Alias for channel 8 CTRL register
ch8_al1_read_addr: CH8_AL1_READ_ADDR0x214 - Alias for channel 8 READ_ADDR register
ch8_al1_write_addr: CH8_AL1_WRITE_ADDR0x218 - Alias for channel 8 WRITE_ADDR register
ch8_al1_trans_count_trig: CH8_AL1_TRANS_COUNT_TRIG0x21c - Alias for channel 8 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch8_al2_ctrl: CH8_AL2_CTRL0x220 - Alias for channel 8 CTRL register
ch8_al2_trans_count: CH8_AL2_TRANS_COUNT0x224 - Alias for channel 8 TRANS_COUNT register
ch8_al2_read_addr: CH8_AL2_READ_ADDR0x228 - Alias for channel 8 READ_ADDR register
ch8_al2_write_addr_trig: CH8_AL2_WRITE_ADDR_TRIG0x22c - Alias for channel 8 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch8_al3_ctrl: CH8_AL3_CTRL0x230 - Alias for channel 8 CTRL register
ch8_al3_write_addr: CH8_AL3_WRITE_ADDR0x234 - Alias for channel 8 WRITE_ADDR register
ch8_al3_trans_count: CH8_AL3_TRANS_COUNT0x238 - Alias for channel 8 TRANS_COUNT register
ch8_al3_read_addr_trig: CH8_AL3_READ_ADDR_TRIG0x23c - Alias for channel 8 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch9_read_addr: CH9_READ_ADDR0x240 - DMA Channel 9 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch9_write_addr: CH9_WRITE_ADDR0x244 - DMA Channel 9 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch9_trans_count: CH9_TRANS_COUNT0x248 - DMA Channel 9 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch9_ctrl_trig: CH9_CTRL_TRIG0x24c - DMA Channel 9 Control and Status
ch9_al1_ctrl: CH9_AL1_CTRL0x250 - Alias for channel 9 CTRL register
ch9_al1_read_addr: CH9_AL1_READ_ADDR0x254 - Alias for channel 9 READ_ADDR register
ch9_al1_write_addr: CH9_AL1_WRITE_ADDR0x258 - Alias for channel 9 WRITE_ADDR register
ch9_al1_trans_count_trig: CH9_AL1_TRANS_COUNT_TRIG0x25c - Alias for channel 9 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch9_al2_ctrl: CH9_AL2_CTRL0x260 - Alias for channel 9 CTRL register
ch9_al2_trans_count: CH9_AL2_TRANS_COUNT0x264 - Alias for channel 9 TRANS_COUNT register
ch9_al2_read_addr: CH9_AL2_READ_ADDR0x268 - Alias for channel 9 READ_ADDR register
ch9_al2_write_addr_trig: CH9_AL2_WRITE_ADDR_TRIG0x26c - Alias for channel 9 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch9_al3_ctrl: CH9_AL3_CTRL0x270 - Alias for channel 9 CTRL register
ch9_al3_write_addr: CH9_AL3_WRITE_ADDR0x274 - Alias for channel 9 WRITE_ADDR register
ch9_al3_trans_count: CH9_AL3_TRANS_COUNT0x278 - Alias for channel 9 TRANS_COUNT register
ch9_al3_read_addr_trig: CH9_AL3_READ_ADDR_TRIG0x27c - Alias for channel 9 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch10_read_addr: CH10_READ_ADDR0x280 - DMA Channel 10 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch10_write_addr: CH10_WRITE_ADDR0x284 - DMA Channel 10 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch10_trans_count: CH10_TRANS_COUNT0x288 - DMA Channel 10 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch10_ctrl_trig: CH10_CTRL_TRIG0x28c - DMA Channel 10 Control and Status
ch10_al1_ctrl: CH10_AL1_CTRL0x290 - Alias for channel 10 CTRL register
ch10_al1_read_addr: CH10_AL1_READ_ADDR0x294 - Alias for channel 10 READ_ADDR register
ch10_al1_write_addr: CH10_AL1_WRITE_ADDR0x298 - Alias for channel 10 WRITE_ADDR register
ch10_al1_trans_count_trig: CH10_AL1_TRANS_COUNT_TRIG0x29c - Alias for channel 10 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch10_al2_ctrl: CH10_AL2_CTRL0x2a0 - Alias for channel 10 CTRL register
ch10_al2_trans_count: CH10_AL2_TRANS_COUNT0x2a4 - Alias for channel 10 TRANS_COUNT register
ch10_al2_read_addr: CH10_AL2_READ_ADDR0x2a8 - Alias for channel 10 READ_ADDR register
ch10_al2_write_addr_trig: CH10_AL2_WRITE_ADDR_TRIG0x2ac - Alias for channel 10 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch10_al3_ctrl: CH10_AL3_CTRL0x2b0 - Alias for channel 10 CTRL register
ch10_al3_write_addr: CH10_AL3_WRITE_ADDR0x2b4 - Alias for channel 10 WRITE_ADDR register
ch10_al3_trans_count: CH10_AL3_TRANS_COUNT0x2b8 - Alias for channel 10 TRANS_COUNT register
ch10_al3_read_addr_trig: CH10_AL3_READ_ADDR_TRIG0x2bc - Alias for channel 10 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch11_read_addr: CH11_READ_ADDR0x2c0 - DMA Channel 11 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
ch11_write_addr: CH11_WRITE_ADDR0x2c4 - DMA Channel 11 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
ch11_trans_count: CH11_TRANS_COUNT0x2c8 - DMA Channel 11 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
ch11_ctrl_trig: CH11_CTRL_TRIG0x2cc - DMA Channel 11 Control and Status
ch11_al1_ctrl: CH11_AL1_CTRL0x2d0 - Alias for channel 11 CTRL register
ch11_al1_read_addr: CH11_AL1_READ_ADDR0x2d4 - Alias for channel 11 READ_ADDR register
ch11_al1_write_addr: CH11_AL1_WRITE_ADDR0x2d8 - Alias for channel 11 WRITE_ADDR register
ch11_al1_trans_count_trig: CH11_AL1_TRANS_COUNT_TRIG0x2dc - Alias for channel 11 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch11_al2_ctrl: CH11_AL2_CTRL0x2e0 - Alias for channel 11 CTRL register
ch11_al2_trans_count: CH11_AL2_TRANS_COUNT0x2e4 - Alias for channel 11 TRANS_COUNT register
ch11_al2_read_addr: CH11_AL2_READ_ADDR0x2e8 - Alias for channel 11 READ_ADDR register
ch11_al2_write_addr_trig: CH11_AL2_WRITE_ADDR_TRIG0x2ec - Alias for channel 11 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
ch11_al3_ctrl: CH11_AL3_CTRL0x2f0 - Alias for channel 11 CTRL register
ch11_al3_write_addr: CH11_AL3_WRITE_ADDR0x2f4 - Alias for channel 11 WRITE_ADDR register
ch11_al3_trans_count: CH11_AL3_TRANS_COUNT0x2f8 - Alias for channel 11 TRANS_COUNT register
ch11_al3_read_addr_trig: CH11_AL3_READ_ADDR_TRIG0x2fc - Alias for channel 11 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel.
intr: INTR0x400 - Interrupt Status (raw)
inte0: INTE00x404 - Interrupt Enables for IRQ 0
intf0: INTF00x408 - Force Interrupts
ints0: INTS00x40c - Interrupt Status for IRQ 0
inte1: INTE10x414 - Interrupt Enables for IRQ 1
intf1: INTF10x418 - Force Interrupts for IRQ 1
ints1: INTS10x41c - Interrupt Status (masked) for IRQ 1
timer0: TIMER00x420 - Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
timer1: TIMER10x424 - Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
multi_chan_trigger: MULTI_CHAN_TRIGGER0x430 - Trigger one or more channels simultaneously
sniff_ctrl: SNIFF_CTRL0x434 - Sniffer Control
sniff_data: SNIFF_DATA0x438 - Data accumulator for sniff hardware\n Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
fifo_levels: FIFO_LEVELS0x440 - Debug RAF, WAF, TDF levels
chan_abort: CHAN_ABORT0x444 - Abort an in-progress transfer sequence on one or more channels
n_channels: N_CHANNELS0x448 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
ch0_dbg_ctdreq: CH0_DBG_CTDREQ0x800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch0_dbg_tcr: CH0_DBG_TCR0x804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch1_dbg_ctdreq: CH1_DBG_CTDREQ0x840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch1_dbg_tcr: CH1_DBG_TCR0x844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch2_dbg_ctdreq: CH2_DBG_CTDREQ0x880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch2_dbg_tcr: CH2_DBG_TCR0x884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch3_dbg_ctdreq: CH3_DBG_CTDREQ0x8c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch3_dbg_tcr: CH3_DBG_TCR0x8c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch4_dbg_ctdreq: CH4_DBG_CTDREQ0x900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch4_dbg_tcr: CH4_DBG_TCR0x904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch5_dbg_ctdreq: CH5_DBG_CTDREQ0x940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch5_dbg_tcr: CH5_DBG_TCR0x944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch6_dbg_ctdreq: CH6_DBG_CTDREQ0x980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch6_dbg_tcr: CH6_DBG_TCR0x984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch7_dbg_ctdreq: CH7_DBG_CTDREQ0x9c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch7_dbg_tcr: CH7_DBG_TCR0x9c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch8_dbg_ctdreq: CH8_DBG_CTDREQ0xa00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch8_dbg_tcr: CH8_DBG_TCR0xa04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch9_dbg_ctdreq: CH9_DBG_CTDREQ0xa40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch9_dbg_tcr: CH9_DBG_TCR0xa44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch10_dbg_ctdreq: CH10_DBG_CTDREQ0xa80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch10_dbg_tcr: CH10_DBG_TCR0xa84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
ch11_dbg_ctdreq: CH11_DBG_CTDREQ0xac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
ch11_dbg_tcr: CH11_DBG_TCR0xac4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
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